Method of fabricating an integrated circuit to improve soft...

Details Method of fabricating an integrated circuit to improve soft... Method of fabricating an integrated circuit to improve soft...

2007-06-19

2007-06-19

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C326S010000

Reexamination Certificate

active

11030273

ABSTRACT:
The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

REFERENCES:
patent: 6794908 (2004-09-01), Erstad
patent: 2005/0156620 (2005-07-01), Carlson
patent: 2005/0179093 (2005-08-01), Morris
Hubert, G., et al. “Detailed Analysis of Secondary Ions' effect on the Calculation of Neutron—SRAMS”, IEEE Trans. Nuclear Science, vol. 48, issue 6, Dec. 2001, pp. 1953-1959.

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