Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
2002-09-17
2004-06-01
Chambliss, Alonzo (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S113000, C438S458000, C438S460000, C438S622000, C029S841000, C029S855000
Reexamination Certificate
active
06743661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor packaging, and more particularly to a packaging configuration capable of carrying a high density of transmission line structures that can be bonded directly to a printed wiring board.
2. Description of the Related Art
There are a very large number of integrated circuit packages on the market. Generally speaking the packaging process is a separate activity from production of the active die, and typically carried out by a packaging contractor. Packages are purchased by assembly contractors where product circuit boards are completed. Since these assembly contractors generally lack the technology to attach silicon die directly to a circuit board packaging contractors have provided this service. Attaching the silicon die is often done by ultrasonic wire bonding of pads on the integrated circuit (IC) to a lead frame. A hermetically sealed package, frequently plastic, is used to enclose the IC. In a final step the leads are cut and formed into pins forming the classic dual inline package as illustrated in block diagram
100
of FIG.
1
. As IC technology has progressed there has been a move towards surface mounting packages with a high density of connections at the package periphery, such as the quad flat pack outline illustrated in block diagram
102
of FIG.
2
.
Further increases in pin counts have forced two major changes. Firstly, there is a need for more than one row of contacts at the periphery of the device, as otherwise the pitch of the connections is too small for a reasonably strong bond to a circuit board to be formed by wire bonding processes. Secondly, the number of contacts to the chip is so large that wire bonding is becoming uneconomical. This has led to the development of the ball grid array and the flip chip packaging designs. Both technologies use solder balls, which are connected to the package or die. Heat is used to reflow the solder to make contact to the mating part, either a printed circuit board (PCB) or an interposer.
Because of the large thermal expansion difference between silicon and typical circuit boards, most packages use a substrate or interposer to redistribute the bonds from the die to the solder balls. More advanced packages may include several layers of wiring in the interposer along with integrated passives. The connection between the interposer (which is usually made of a laminate material) and the die has to take account of thermal expansion mismatch between the silicon and the interposer. There are a large number of ways of making the connection ranging from the traditional wirebond, through flip chip connections via solder balls as mentioned above (using an underfill adhesive to relieve the thermally induced strain in the balls), to micromachined fingers that can be bonded via conductive adhesive to the interposer. The purpose of the interposer is partly to provide for redistribution of wires, but also it allows a package with thermal expansion coefficient similar to the PCB to be provided to the assembly house. Therefore, the burden of accommodating the thermal mismatch between the die and the laminate is borne by the packager, not by the assembly contractor who generally has neither the skills nor the time to consider such matters.
A typical modern package is the flip-chip ball grid array (FCBGA) illustrated as block diagram
110
of FIG.
3
. The FCBGA consists of a ceramic or plastic substrate that has an area array of solder balls
118
(typically composed of an eutectic alloy of tin and lead) for attachment to a circuit board. The semiconductor chip
112
is connected to the substrate
114
through solder bumps
116
in conjunction with an epoxy underfill between the chip
112
and the substrate
114
.
Unfortunately, the technology available to process wiring on laminate material is less sophisticated than that used to develop the active silicon die. The thermal stability, dimensional stability, tendency to outgas contaminants, and other properties of laminate restrict the wiring that can be applied. However, one problem with a package using a non-laminate interposer is that the package must accommodate the thermal expansion differences between the selected interposer and a PCB. Most hard materials useful for high-precision processing have thermal expansion coefficients much less than that of the printed circuit board, thereby making the materials unsuitable as an interposer.
Another problem also related to the production of high speed integrated circuits is that the delays in on-die interconnects continue to increase as semiconductor device features shrink. In turn, the lines used for global interconnects continue to shrink in size along with the scaling of the chip. Because of the increasing RC delay (which is only partially offset by the shift to copper conductors and low-k dielectrics), a large number of repeaters, i.e., non-inverting buffer amplifiers, must be inserted into the global interconnect lines. These repeaters recover the integrity of the signal but at a cost of the gate delay in the repeater. As a result the speed of propagation in on-chip wires is expected to be steady at 40 ps/mm length in optimally repeatered wires.
FIG. 4
illustrates graph
120
displaying the generally known relationship between relative signal delay vs. the process technology node. Each curve has been normalized to show the relative change in signal delay for different classes of interconnect. Line
122
represents the relative delays of global interconnects without repeaters, line
124
represents global interconnects with repeaters, line
126
represents local interconnects and line
128
represents gate delay (fan out
4
) The gate delay represents the delay due to the transistor switching speed. Local interconnects are used to span clusters of a few transistors and are short compared with global interconnects. Moreover, the repeaters themselves are difficult to fabricate since connections must be made from top level metal to the transistor. In addition, the repeaters consume considerable power.
The velocity of wave propagation in an LC transmission line made in surroundings with relative dielectric constant ∈
r
=2.7 is about 5 ps/mm, eight times faster than that in a repeatered line; but such lines must have a total resistance significantly less than the impedance of the transmission line. The practical limits on this impedance are 30-100 ohms. From this, it can be shown that a copper conductor 2 cm long should be at least 2.7 microns per side at low frequencies, rising to at least 5 microns at about 10 gigahertz (GHz) because of skin effects.
FIG. 5
illustrates graph
130
representing the critical wire size for a square copper wire 2 cm long where Z=60&OHgr;. Furthermore, to make a transmission line, the conductor must be in a well-controlled relationship with a grounded surface, and the necessary space between the conductor and this grounded surface further increase the space needed for the whole transmission line. Standard IC fabrication techniques are not well suited for these large structures because a considerable metal and dielectric thickness (~10 &mgr;m) is needed. Many IC techniques are optimized for the 0.1-1 &mgr;m thickness regime. Thicker layers may be better fabricated by lower cost techniques. However, the density of such interconnects, and the requirements for reasonable precision of spacing between the conductor and ground return path, means that printed circuit board technology is also unsuitable. The correct length scale lies between the PCB and high-end IC technology, in the length scales associated with magnetic disk head technology and micro-machine production.
Naeemi in “Performance improvement using on-board wires for on-chip interconnects,” IEEE, October 2000, pp. 325-328, has shown that for future microprocessors the number of global interconnects longer than a few cm is limited to a few thousand. In a die projected to be as large as 40 mm per side, the number of lines pins needed
Chambliss Alonzo
Martine & Penilla LLP
Novellus Systems Inc.
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