Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-07-25
2000-08-22
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438682, 438683, H01L 214763
Patent
active
061071943
ABSTRACT:
The present invention provides improved device speed by using two silicides with two different compositions: one silicide is overlaid on a polysilicon gate layer, to form a "polycide" layer with improved sheet resistance, and the other is clad on at least some "active" areas of the monocrystalline silicon, to form a "salicided" active area with improved sheet and contact resistance. Preferably one silicide is a reaction product and the other is deposited.
REFERENCES:
patent: 4080719 (1978-03-01), Wilting
patent: 4102733 (1978-07-01), De La Moneda et al.
patent: 4128670 (1978-12-01), Gaebssien
patent: 4253907 (1981-03-01), Parry et al.
patent: 4354896 (1982-10-01), Hunter et al.
patent: 4356623 (1982-11-01), Hunter
patent: 4384938 (1983-05-01), Desilets et al.
patent: 4398335 (1983-08-01), Lehrer
patent: 4443930 (1984-04-01), Hwang et al.
patent: 4470189 (1984-09-01), Roberts et al.
patent: 4543271 (1985-09-01), Peters
patent: 4622735 (1986-11-01), Shibata
patent: 4654112 (1987-03-01), Douglas et al.
patent: 4656732 (1987-04-01), Teng et al.
patent: 4657628 (1987-04-01), Holloway et al.
patent: 4660278 (1987-04-01), Teng
patent: 4675073 (1987-06-01), Douglas
patent: 4686000 (1987-08-01), Heath
patent: 4707218 (1987-11-01), Giammarco et al.
patent: 4715109 (1987-12-01), Bridges
patent: 4721548 (1988-01-01), Morimoto
patent: 4755476 (1988-07-01), Bohm et al.
patent: 4788160 (1988-11-01), Havemann et al.
patent: 4792534 (1988-12-01), Tsuji et al.
patent: 4801350 (1989-01-01), Mattox et al.
patent: 4801560 (1989-01-01), Wood et al.
patent: 4810666 (1989-03-01), Taji
patent: 4818335 (1989-04-01), Karnett
patent: 4824767 (1989-04-01), Chambers et al.
patent: 4894351 (1990-01-01), Batty
patent: 4912061 (1990-03-01), Nasr
patent: 4962414 (1990-10-01), Liou et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 4988423 (1991-01-01), Yamamoto et al.
patent: 4994402 (1991-02-01), Chiu
patent: 4996167 (1991-02-01), Chen
patent: 5003062 (1991-03-01), Yen
patent: 5027185 (1991-06-01), Liauh
patent: 5034348 (1991-07-01), Hartswick et al.
patent: 5059554 (1991-10-01), Spinner et al
patent: 5061646 (1991-10-01), Sivan et al.
patent: 5063176 (1991-11-01), Lee et al.
patent: 5110763 (1992-05-01), Matsumoto
patent: 5117273 (1992-05-01), Stark et al.
patent: 5158910 (1992-10-01), Cooper et al.
patent: 5166088 (1992-11-01), Ueda et al.
patent: 5174858 (1992-12-01), Yamamoto et al.
patent: 5200808 (1993-04-01), Koyama et al.
patent: 5214305 (1993-05-01), Huang et al.
patent: 5244841 (1993-09-01), Marks et al.
patent: 5250472 (1993-10-01), Chen et al.
patent: 5254867 (1993-10-01), Fukuda et al.
patent: 5256895 (1993-10-01), Bryant et al.
patent: 5260229 (1993-11-01), Hodges et al.
patent: 5266516 (1993-11-01), Ho
patent: 5266525 (1993-11-01), Morozumi
patent: 5310720 (1994-05-01), Shin et al.
patent: 5320983 (1994-06-01), Ouellet
patent: 5323047 (1994-06-01), Nguyen
patent: 5380553 (1995-01-01), Loboda
patent: 5411917 (1995-05-01), Forouhi et al.
patent: 5439846 (1995-08-01), Nguyen et al.
Jones, N.J. et al., "Salicide with buried silicide layer," IBM Technical Disclosure Bulletin, 27(2), Jul. 1984, pp. 1044-1045.
Wolf et al., "Silicon processing for the VLSI era," vol. 1, Lattice Press, 1986, pp. 384-399.
Wolf et al., "Silicon processing for the VLSI era," vol. 2, Process Integration, 1990 Lattice Press, pp. 273-275.
Murarka, S.P., "Silicides for VLSI applications," 1983, Academic Press, pp. 164-167.
H.T.G. Hentzell et al., "Formation of aluminum silicide between two layers of amorphous silicon," Applied Physics Letters, vol. 50, No. 14, pp. 933-934, Apr. 1987.
M. Lin et al., "An environment-insensitive trilayer structure for titanium silicide formation," Journal of Electrochem. Soc., vol. 133, No. 11, pp. 2386-2389, Nov. 1986.
S. Saitoh et al., "Formation of a double-hetero Si/CoSi.sub.2 /Si structure using molecular beam and solid phase expitaxies," Jap. J. of Applied Physics, vol. 20, pp. 49-54, 1981.
J.K. Howard, "High conductivity transition metal silicide (NbSi.sub.2) for FET gate structures," IBM Technical Journal, vol. 22, No. 2, Jul. 1979.
Singer, "A new technology for oxide contact and via etch," Semiconductor Int'l, p. 36 (1993).
Gambino et al., "A Si.sub.3 N.sub.4 etch stop for borderless contacts in 0.25 .mu.m devices," VMIC Conference, p. 558 (1995).
"Methods of forming small contact holes," IBM Technical Disclosure Bulletin, vol. 30, No. 8 (1988).
"Method to produce sizes in openings in photo images smaller than lithographic minimum size," IBM Technical Disclosure Bulletin, vol. 29, No. 3 (1986).
Ishagaki, et al., "Low parasitic resistance technologies with NES-SAC and SWT-CVD process for low supply voltage, high speed BiCMOS SRAMs," 1994 Symposium on VLSI Technology Digest of Technical Papers, p. 99 (1994).
T. Fukase, et al., "A margin-free contact process using an AI.sub.2 O.sub.2 etch-stop layer for high density devices," IEDM, p. 837 (1992).
Armacos, et al., "Selective oxide
itride dry etching in a high density plasm reactor," Extended Abstracts, vol. 93-1, Spring Meeting (1993).
Lau, et al., "A super self-aligned source/drain MOSFET," IEDM, p. 358, (1987).
Wehner, et al., "The nature of physical sputtering," Handbook of Thin Film Technology, p. 3-1, McGraw-Hill (1970).
L.M. Ephrath and G.S. Mathad, "Etching-applications and trends of dry etching," in Handbook of Advanced Technology and Computer Systems at 27ff (ed. G. Rabbat 1988).
Device Physics (4 Handbook of Semiconductors) pp. 208-209ff (ed. C. Hilsum 1981).
B. Gorowitz and R. Saia, "Reactive ion etching," in 8 VLSI Electronics at 297ff (ed. N. Einspruch and D. Brown 1984).
A. Schiltz, "Advantages of using spin on glass layer in interconnection dielectric planarization" Microelectronic Engineering, vol. 5, pp. 413-421 (1986).
S. Ghandhi, VLSI Fabrication Principles, Wiley.
Patent Abstracts of Japan, vol. 10, No. 103 (E-398, Apr. 23, 1986 and JP-A-60 246 675 Seiko Denshi Kogyo K.K.), Dec. 6, 1985.
Patent Abstracts of Japan, vol. 17, No. 401 (E-1404, Jul. 27, 1993, and JP-A-05 074 958 NEC Corp.) Mar. 26, 1993.
Patent Abstracts of Japan, vol. 16, No. 526 (E-1286, Oct. 28, 1992, and JP-A-04 196 486 Toshiba Corp.) Jul. 16, 1992.
"Plasma etch anisotropy," J. Electrochem. Soc.: Solid-State Science & Technology, C.B. Zarowin, May 1983, pp. 1144-1152.
J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, "Polysilicon planarization using spin-on glass," S. Ramaswami & A. Nagy, pp. 591, 599.
J. Electrochem. Soc., vol. 139, No. 2, Feb. 1992, "Three low Dt options for planarizing the premetal dielectric on an advanced double poly BiCMOS process," by W. Dauksher, M. Miller and C. Tracy, pp. 532-536.
J. Electrochem. Soc., vol. 140, No. 4, Feb. 1993, "The effect of plasma cure temperature on spin-on glass," by H. Namatsu and K. Minegishi, pp. 1121-1125.
IEEE Electron Device Letters, vol. 12, No. 3, Mar. 1991, "Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric," N. Lifshitz and G. Smolinsky, pp. 140-142.
Journal of Electrochemical Society, vol. 138, No. 10, Oct. 1991, Manchester, New Hampshire, U.S., pp. 3019-3024, K. Fujino et al., "Doped silicon oxide deposition by atmospheric pressure and low temperature chemical vapor deposition using tetraethoxysilane and ozone".
Patent Abstracts of Japan, vol. 11, No. 77 (E-487, Mar. 1987, and JP-A-61 232 646 NEC Corp.) Oct. 16, 1986.
Patent Abstracts of Japan, vol. 16, No. 318 (E-1232, Jul. 13, 1992, and JP-A-40 92 453 Seiko Epson Corp.) Mar. 25, 1992.
Patent Abstracts of Japan, vol. 15, No. 348 (E-1107, Sep. 4, 1991, and JP-A-31 33 131 Mitsubishi Electric Corp.) Jun. 6, 1991.
Proceedings of the International Devices Meeting, Washington, Dec. 5-8, 1993, Dec. 5, 1993, Institute of Electrical and Electronics Engineers, pp. 441-444, Surbanna S. et al., "A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic".
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, New York, USA, pp.344-345, "Method for reducing the diffusion contact borders".
Hodges Robert Louis
Nguyen Loi Ngoc
Everhart Caridad
Galanthay Theodore E.
Jorgenson Lisa K.
STMicroelectronics Inc.
Venglarik Dan
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