Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2000-02-11
2002-04-09
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
Reexamination Certificate
active
06368900
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a programmable antifuse element, to be used as a vehicle in the replacement of defective components, with spare or replacement components.
(2) Description of Prior Art
Antifuse elements have been used to allow defective regions, in a body of array devices, to be replaced with adjacent, spare device arrays. This is accomplished by placing a programmable antifuse element, between the main body of gate arrays, and a region comprised of replacement gate arrays. The antifuse element is comprised of a high resistance material, such as amorphous silicon, resulting in an “off” state. The high resistance, amorphous silicon layer, although physically connected to both the main body of gate arrays, and the region of replacement arrays, is not electrically connected due its high resistance. A high voltage pulsing procedure, results in the conversion of the high resistance amorphous silicon layer to a low resistance layer, resulting in the “on” state, featuring electrical, as well as physical connection to both the main body of gate arrays, and to the region of spare gate arrays.
One method of providing physical connection between the main body of gate arrays, and the adjacent region of spare gate arrays, is via use of a tungsten plug structure, located between these regions, with the antifuse element overlying the tungsten plug structure. Pulsing of the high resistance, antifuse element results in the desired electrical connection between the main body of gate arrays, and the region of spare gate arrays, physically via the tungsten plug structure, and electrically via conversion of the high resistance amorphous silicon layer to a low resistance material. However the high voltage pulse, applied to a region of the antifuse element, can result in current and field crowding, at the sharp edges of the underlying tungsten plug structure, which in turn results in excess joule heating and non-uniform melting of the antifuse element. The non-uniform melting, in turn results in non-uniform conversion of the antifuse element from the high resistance layer, to the desired low resistance layer.
This invention will describe a novel process sequence in which the current crowding, at the sharp edges of the tungsten plug structure, and the subsequent, excess joule heating of the antifuse element, is avoided via the formation of conductive spacers, on the sides of a protruding tungsten plug structure. First the insulator layer, in which the tungsten plug structure is inlaid in, is etched back, resulting in a tungsten plug structure, which protrudes from the top surface of the insulator layer. This allows subsequent conductive spacers to be formed on the sides of the portion of the tungsten plug structure that is protruding, resulting in a smooth edge for the spacer covered, tungsten plug structure. In addition to protecting, or smoothing the edges of the tungsten plug structure, to alleviate the effects of the high voltage pulsing, the protruding portions of the tungsten plug structure provide additional surface area for contact by overlying layers, thus reducing interface resistance. Prior art, such as Hawley et al, in U.S. Pat. No. 5,920,109, as well as Hawley et al, in U.S. Pat. No. 5,804,500, describe methods for forming raised, or protruding, tungsten plug structures, for use in combination with antifuse elements, however that prior art does not teach the use of the smoothing, conductive spacers, on the sides of the raised tungsten plug structures, needed to avoid current and field crowding, at the sharp edges of the tungsten plug structure, during the high voltage pulsing applied to the antifuse element.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a amorphous silicon, antifuse element, as a vehicle to allow replacement of defective regions of a main body of gate arrays, with replacement or spare gate arrays.
It is another object of this invention to use a tungsten plug structure, located in a via hole in an insulator layer, between the main body of gate arrays, and the region of replacement gate arrays.
It is still another object of this invention to etch back the insulator layer, in which the tungsten plug structure resides in, then to form smooth, conductive spacers, on the sides of the raised, or protruding, tungsten plug structure.
It is still yet another object of this invention to form the amorphous silicon, antifuse element, overlying the raised tungsten plug structure, and the smooth, conductive spacers, on the sides of the tungsten plug structure.
In accordance with the present invention a method for forming an antifuse element, on a raised, or protruding, tungsten plug structure, which in turn is located between the main body of gate arrays, and a region of replacement arrays, and featuring conductive spacers formed on the sides of the raised tungsten plug, is described. A first insulator layer is formed on an underlying conductive region, which can be comprised of a main body of gate arrays, or of a conductive layer which directly contacts the main body of gate arrays. A via hole is formed in the first insulator layer, exposing a portion of the top surface of the underlying conductive region, followed by the formation of a tungsten plug structure, in the via hole. A selective etch is used to remove a top portion of the first insulator layer, resulting in a portion of the tungsten plug structure protruding upwards from the top surface of the first insulator layer. Conductive spacers are next formed on the sides of the raised, or protruding portion of tungsten plug structure, resulting in smooth edges for the conductive spacer—tungsten plug structure. An amorphous silicon layer is next deposited, overlying the raised tungsten plug structure, followed by the deposition of a titanium nitride barrier layer. After definition of the titanium nitride, and the amorphous silicon layers, forming the antifuse structure, a second insulator layer is deposited. After formation of a via hole in the second insulator layer, exposing a portion of the top surface of the titanium nitride—amorphous silicon, antifuse structure, a conductive region, comprised of either a region of replacement gate arrays, or a conductive layer directly interfacing with the region of replacement gate arrays, is formed in the via hole, located in the second insulator layer, overlying, and contacting the titanium nitride—amorphous silicon structure.
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Kenkaraseril John Prasao
Mukhopadhyay Madhusudan
Teo Yeow-Meng
Xiang Qi Dong
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