Method of fabricating a wafer level package

Details Method of fabricating a wafer level package Method of fabricating a wafer level package

2001-12-18

2004-03-02

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S462000

Reexamination Certificate

active

06699782

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor package, and more particularly to, a fabrication method for a wafer level package capable of simplifying package fabricating processes by reducing the number of metal sputtering processes for the formation of metal wiring and stably adhering a conductive ball by maximizing the contact area of conductive ball and metal wiring.
2. Description of the Related Art
As generally known, semiconductor devices, such as integrated circuits (IC), generally are mounted in a package. The package is formed by sawing IC chips, obtained by a layer growth process of a semiconductor wafer, from the wafer and then shielding and molding the separated IC chip for protection from external moisture and impurities. Leads are attached to the structure to connect with circuitry external to the package, thereby completing the package process.
Semiconductor packages are generally classified according to the method used in the leads and in the shield or molding structure. A wafer level package of the present invention has a molding structure wherein the IC chip is of a size that takes up most of space of the package. This type of wafer level package is employed in micro device to increase packaging density and the degree of integration.
FIGS. 1A
to
1
D illustrate the steps for fabrication in a conventional method for fabricating a wafer level package.
Referring to
FIG. 1A
, a first insulating layer
116
is deposited on a semiconductor substrate
100
and then, exposure and development processes are performed by photolithography to form a first opening
117
exposing a chip pad
112
.
On the upper part of the semiconductor substrate
100
, a plurality of such chip pads
112
are formed, separated from each other, and a protective layer
114
is formed between the chip pads
112
.
Although it is not shown in drawings, a plurality of diffusion areas, gate electrodes, electrodes for the formation of capacity and metal wiring are connected to chip pads.
Referring to
FIG. 1B
, metal material, such as aluminum, is deposited on the first insulating layer
116
in accordance with a sputtering method and then pattern etched to cover the first opening
117
and be connected to chip pad
112
, thereby obtaining metal wiring
118
.The metal wiring
118
is connected to chip pad
112
and a predetermined part thereof is extended. On the extended part, a ball land (not shown) is formed by succeeding processes to provide a connection to which a conductive ball is later adhered.
Referring to
FIG. 1C
, a second insulating layer
120
is deposited on the first insulating layer
116
to cover the metal wiring
118
. Then, the second insulating layer
120
is subjected to exposure and development processes by photolithography, thereby obtaining a second opening
121
to form the ball land.
Referring to
FIG. 1D
, a conductive ball
130
, such as solder ball, is adhered to the metal wiring
118
at the second opening
121
, thereby completing package fabrication.
However, there is a problem in that the contact area of the metal wiring and the conductive ball is small, since metal wiring under the conductive ball has a flat structure. Furthermore, when a thermal cycle is performed to test reliability of the package, splits are generated on the contact area of the conductive ball and the metal wiring due to thermal expansion. Here, as the contact area is increased, a higher energy level is required to generate such splits. Therefore, an extensive contact area has been found effective to prevent the generation of splits. As a result, the above-mentioned conventional method has a disadvantage of package reliability as a result of the contact area being small.
As a solution to these problems, a method has been proposed that the metal wiring have an uneven shape so as to increase the contact area of the metal wiring and the conductive ball.
FIGS. 2A
to
2
E are drawings for showing the steps for fabrication of a wafer level package according to another conventional method. Referring to
FIG. 2A
, a first insulating layer
216
is deposited on a semiconductor substrate
200
and then pattern etching is performed to expose a chip pad
212
, thereby forming a first opening
217
. In the drawing, reference code
214
indicates a protective layer.
The semiconductor substrate
200
may be the same as semiconductor substrate
100
of the above-mentioned conventional method.
Referring to
FIG. 2B
, a metal layer is deposited on the first insulating layer
216
by sputtering aluminum and then pattern etching is performed to cover the first opening
217
, thereby forming a first metal wiring
218
.
Next, referring to
FIG. 2C
, a second insulating layer
220
is deposited on the first insulating layer
216
so as to cover the first metal wiring
218
. Then, a predetermined part of the second insulating layer
220
is etched to form a second opening
221
for the formation of a ball land.
Referring to
FIG. 2D
, a second metal wiring
222
is formed on the second insulating layer
220
by sputtering aluminum and then performing an etching process to cover the second opening
221
. The second metal wiring
222
is connected to the chip pad
212
through the first metal wiring
218
.
Finally, referring to
FIG. 2E
, a conductive ball
230
is adhered on the second metal wiring
222
, thereby completing package fabrication.
However, according to the above method, sputtering processes are required to be performed twice and, as a result, package fabrication processes become complicated because of the need to transfer into another chamber for another metal formation.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above-mentioned problems. One object of the present invention is to provide a fabrication method for a wafer level package capable of increasing reliability by maximizing the contact area of a conductive ball and of the metal wiring.
Another object of the present invention is to provide a fabrication method of wafer level package capable of simplifying the fabrication steps and processes by performing a metal sputtering process only once. In order to accomplish the above objects, the present invention comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer having a first opening exposing chip pads and a second opening forming a ball land on the substrate; forming a metal wiring connected to the chip pad through the first opening and covering the second opening to provide a ball land on the first insulating layer; forming a second insulating layer having a third opening which covers the metal wiring, except for the third opening so as to expose the ball land; and adhering a conductive ball to the metal wiring exposed by the third opening, the conductive ball being in contact with the sides of the third opening.
According to the present invention, a second embodiment comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer having a first opening thereon to expose the chip pad on the substrate; performing an etching process by irradiating laser energy on a predetermined part of the first insulating layer to form a second opening for the formation of a ball land; forming metal wiring connected to the chip pad through the first opening on the first insulating layer and covering the second opening to provide a ball land; forming a second insulating layer having a third opening which covers the metal wiring, except for the third opening so as to expose the ball land; and adhering a conductive ball to the metal wiring exposed by the third opening, the conductive ball being in contact with the sides of the third opening.
According to the present invention, a third embodiment comprises the steps of: providing a substrate having a plurality of chip pads on the upper part thereof; forming a first insulating layer

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