Method of fabricating a vertical insulated gate transistor...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S302000, C257S329000, C257S330000, C257S344000, C257S408000

Reexamination Certificate

active

06861684

ABSTRACT:
The vertical transistor includes, on a semiconductor substrate, a vertical pillar5having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer7situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region800resting on the gate dielectric layer7and a second region90facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities14S,14D.

REFERENCES:
patent: 5073519 (1991-12-01), Rodder
patent: 5504359 (1996-04-01), Rodder
patent: 5576245 (1996-11-01), Cogan et al.
patent: 5998289 (1999-12-01), Sagnes
patent: 198450031 (2000-02-01), None
patent: 0145567 (1985-06-01), None
patent: 2765245 (1998-12-01), None
patent: WO 9813880 (1998-04-01), None
Preliminary Search Report dated Feb. 4, 2002 for French Application No. 0104436.

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