Method of fabricating a three-dimensional MOSFET employing a...

Details Method of fabricating a three-dimensional MOSFET employing a... Method of fabricating a three-dimensional MOSFET employing a...

2005-03-21

2009-02-24

Smith, Matthew (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S242000, C438S197000, C438S435000

Reexamination Certificate

active

07494895

ABSTRACT:
A method of fabricating a 3D field effect transistor employing a hard mask spacer includes forming a hard mask pattern on a semiconductor substrate. The semiconductor substrate is etched using the hard mask pattern as an etch mask to form a trench that defines an active region. A trench oxide layer and a liner are sequentially formed on the semiconductor substrate, and an isolation layer is formed to fill the trench. An upper surface of the isolation layer may by recessed below an upper surface of the hard mask pattern. A hard mask spacer is formed that covers sidewalls of the hard mask pattern. Some portions of the isolation layer where an etching is blocked by the hard mask spacer remain on sidewalls of the channel region, respectively, thereby preventing the liner from being damaged by etching.

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patent: 6551937 (2003-04-01), Jun et al.
patent: 2003/0141546 (2003-07-01), Maegawa
patent: 2005/0093075 (2005-05-01), Bentum et al.
patent: 2002-0018059 (2002-03-01), None
patent: 2002-0096654 (2002-12-01), None
patent: WO 03/003470 (2003-01-01), None
Wolf et al., “Silicon Processing fo the VLSI Era”, 2000, Lattice Press, 2nd Ed., vol. 1, pp. 202-206.
English language abstract of Korean Publication No. 2002-0018059.
English language abstract of Korean Publication No. 2002-0096654.

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