Method of fabricating a thin film transistor using dual or...

Details Method of fabricating a thin film transistor using dual or... Method of fabricating a thin film transistor using dual or...

2006-03-14

2006-03-14

Wilson, Christian D. (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S150000

Reexamination Certificate

active

07011992

ABSTRACT:
The present invention relates to a method for fabricating a TFT using dual or multiple gates, and provides a TFT having superior characteristics and uniformity by providing a method for fabricating a TFT using dual or multiple gates comprising the steps of calculating probability including Nmax the maximum number of crystal grain boundaries in active channel regions according to the length of the active channels, and adjusting gap between the active channels capable of synchronizing the number of the crystal grain boundaries in each active channel regions of the TFT using the dual or multiple gates in case that Gs size of crystal grains of polycrystalline silicon forming a TFT substrate, θ angle in which “primary” crystal grain boundaries are inclined to a direction perpendicular to an active channel direction of the gates, width of the active channels and length of the active channels are determined.

REFERENCES:
patent: 6177301 (2001-01-01), Jung
patent: 6590230 (2003-07-01), Yamazaki et al.
patent: 6720578 (2004-04-01), Lee
patent: 6759679 (2004-07-01), Lee
patent: 6825494 (2004-11-01), Lee et al.
patent: WO 97/45827 (1997-12-01), None

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