Method of fabricating a tapered via hole in polyimide

Details Method of fabricating a tapered via hole in polyimide Method of fabricating a tapered via hole in polyimide

1987-05-21

1989-05-23

Lacey, David L.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156652, 156653, 1566611, 156668, 437203, 437235, 437947, 437981, H01L 21312

Patent

active

048327883

ABSTRACT:
A method of fabricating a tapered via hole in a polyimide layer of an integrated circuit includes the steps of: disposing a layer of SiO.sub.2 on the polyimide layer and a layer of photoresist on the SiO.sub.2 such that the layers have an opening which exposes a region of the polyimide layer for the via hole; etching the exposed polyimide region partway through the polyimide layer, while simultaneously etching back the photoresist on the sidewalls of the opening to thereby uncover a strip of SiO.sub.2 adjacent to the perimeter of the exposed polyimide region; enlarging the exposed region of the polyimide by etching the uncovered strip of SiO.sub.2 ; and repeating the etching step and enlarging step a predetermined number of times.

REFERENCES:
patent: 4472240 (1984-09-01), Kameyama
patent: 4484979 (1984-11-01), Stocker
patent: 4487652 (1984-12-01), Almgren
patent: 4495220 (1985-01-01), Wolf et al.
patent: 4514252 (1985-04-01), Roland
patent: 4522681 (1985-06-01), Gorowitz et al.
patent: 4560436 (1985-12-01), Bukhman et al.
patent: 4592802 (1986-06-01), Deleonibus et al.

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