Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-04-25
2004-01-06
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S640000, C438S739000, C438S947000, C430S312000
Reexamination Certificate
active
06673714
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of fabricating a sub-lithographic sized via in which a resulting sub-lithographic feature size of the via is less than a lithography limit of a lithographic system. More specifically, the present invention relates to a method of fabricating a sub-lithographic sized via using dual polymer layers with different etch rates to form a via having a sub-lithographic feature size that is is less than a lithography limit of a lithographic system.
BACKGROUND OF THE ART
A standard method in the microelectronics industry for patterning features on a substrate uses well understood photolithographic processes. Typically, a layer of photoresist is coated onto a substrate material followed by exposing the photoresist with a light source through a mask. The mask includes patterned features, such as lines and spaces, that are to be transferred to the photoresist. After the photoresist is exposed, a solvent is used to define the patterns that were transferred to the photoresist. The patterns produced by this process are typically limited to line widths greater than a minimum resolution &lgr; of a photolithographic alignment tool, which is ultimately limited by a wavelength of light of a light source used to expose the photoresist. At present, a state of the art photolithographic alignment tool is capable of printing line widths as small as 100 nm.
Features patterned into the photoresist are transferred into the substrate material using well known semiconductor processes such as reactive ion etching, ion milling, plasma etching, or chemical etching. Using standard semiconductor processing methods, a line width of &lgr; or a grating (i.e. a line-space sequence) with a period of 2&lgr; can be created.
However, in many applications it is advantageous to have the line width or the period be as small as possible. Smaller line widths or periods translate into higher performance and/or higher density circuits. Hence, the microelectronics industry is on a continual quest to reduce the minimum resolution in photolithography systems and thereby reduce the line widths or periods on patterned substrates. The increases in performance and/or density can be of considerable economic advantage because the electronics industry is driven by a demand for faster and smaller electronic devices. A via is just one example of an application in which it is desirable to have a feature size (i.e. a sub-lithographic feature size) that is smaller than the minimum resolution &lgr;.
Consequently, there exists a need for a method of fabricating a sub-lithographic sized via having a features size that is smaller than a minimum resolution of a photolithographic system.
SUMMARY OF THE INVENTION
The method of fabricating a sub-lithographic sized via of the present invention fulfills the aforementioned need for a feature size that is smaller than a minimum resolution of a photolithographic system.
The feature size limitations imposed by the minimum resolution of a photolithographic system are solved by depositing a first polymer layer on an underlying layer followed by depositing a second polymer layer on the first polymer layer. The first polymer layer need not be photo active. On the other hand, the second polymer layer must be photo active so that it can be exposed with a pattern. The second polymer layer is lithographically patterned to define an etch mask therein having a feature size that is within a lithography limit of a lithographic system used to pattern the second polymer layer. An etch process is used to remove all of the first polymer layer except those portions of the first polymer layer that are positioned under the etch mask.
A remaining portion of the first polymer layer has a first etch rate and the second polymer layer (i.e. the etch mask) has a second etch rate. The first etch rate is preselected to be faster than the second etch rate when the first and second polymer layer are isotropically etched. The etch mask and the first polymer layer are isotropically etched so that the first polymer layer dissolves in a substantially lateral direction at a faster rate than the etch mask. The first polymer layer recedes along the surface of the underlying layer defining an exposed surface on the underlying layer and the first polymer layer recedes along the etch mask defining an undercut portion on the etch mask. The isotropic etching is continued until the first polymer layer has dissolved to a sub-lithographic feature size that is less than the lithography limit.
A dielectric layer is then deposited on the exposed portion and on substantially all of the etch mask except the undercut portion. The dielectric layer forms a via sidewall positioned adjacent to the first polymer layer. The etch mask and the first polymer layer are removed by a lift-off process to define a sub-lithographic sized via including a minimum feature size that is substantially equal to the sub-lithographic limit. dr
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a cross-sectional view of a underlying layer according to the present invention.
FIG. 2
is a cross-sectional view depicting a second polymer layer that has been deposited on a first polymer layer according to the present invention.
FIG. 3
is a cross-sectional view of patterning the second polymer layer to define an etch mask therein according to the present invention.
FIGS. 4
a
and
4
b
are cross-sectional views of a first polymer layer positioned under an etch mask according to the present invention.
FIGS. 5 and 6
are cross-sectional views of an isotropic etch of the first polymer layer and the etch mask according to the present invention.
FIGS. 7
a
and
7
b
are cross-sectional views of a dielectric layer deposited on an etch mask and on an exposed portion according to the present invention.
FIGS. 8
a
and
8
b
are cross-sectional views of a sub-lithographic sized via according to the present invention.
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Anthony Thomas C.
Lee Heon
Tran Lung T.
Denny III Trueman H.
Hewlett--Packard Development Company, L.P.
Kielin Erik J.
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