Method of fabricating a strained multi-gate transistor

Details Method of fabricating a strained multi-gate transistor Method of fabricating a strained multi-gate transistor

2007-06-22

2009-02-24

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

On insulating substrate or layer

C438S464000, C438S407000, C438S508000, C438S508000

Reexamination Certificate

active

07494902

ABSTRACT:
A method is disclosed for relaxing strain in a multi-gate device, the method comprising providing a substrate with a strained material, patterning a plurality of fins in the strained material, defining a first region comprising at least one fin, defining a second region comprising at least one fin, providing a diffusion barrier layer on the first region, performing a hydrogen anneal such that the strain in the second region is relaxed.

REFERENCES:
patent: 6562703 (2003-05-01), Maa et al.
patent: 2006/0019464 (2006-01-01), Maa et al.

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