Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2001-07-26
2003-07-15
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S455000
Reexamination Certificate
active
06593204
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a method of fabricating a system comprising a semiconductor substrate and a layer of insulative material on which the substrate rests, i.e., a silicon-on-insulator (SOI) system, and in particular, to a method of obtaining an SOI system including an extremely thin semiconductor layer of excellent uniformity made up of thin semiconductor islets surrounded by an insulative material and resting on a layer of another insulative material.
BACKGROUND OF THE INVENTION
SOI systems are more particularly intended to be used to make devices of the type referred to as “fully depleted” devices in which the charge carriers are fully depleted in the channel area. In such devices the thickness of the semiconductor substrate, also referred to as the active layer, defines the threshold voltage of the MOS transistors and proves to be very important.
A major problem with using fully depleted systems is producing a thin layer of semiconductor substrate on a layer of an insulative material with good control and sufficient reproducibility of the thickness of the active layer between two different systems obtained in the same manner and having the same destination.
To achieve the necessary performance, fully depleted structures would require active layers with a thickness on the order of 5 to 30 nm, depending on the threshold voltage to be obtained and the dimensions of the gates of the transistors. For a track width of 0.1 mm and a threshold voltage of approximately 0.35 volts, for example, the ideal silicon thickness is on the order of 15 nm. Any deficiency in the flatness of the active layer and any difference in thickness of the active layer between two systems leads to a corresponding variation in the threshold voltage. As a general rule, the flatness deficiency on the same active layer is small (on the order of a few percent), but the thickness difference from one system to another can be much greater.
Prior art SOI system fabrication techniques all have a number of drawbacks, in particular these drawbacks include a low production yield, relatively thick active and insulative layers of mediocre uniformity, which are difficult to reproduce from one system to another, and consequently a threshold voltage that is difficult to control.
A first SOI system fabrication method, known as the “SIMOX technology”, includes forming a layer of silicon oxide buried in a silicon substrate by high-dose oxygen implantation followed by annealing at a temperature above 1,300° C. A major drawback of this method is that it requires non-standard equipment. Also, the high-dose oxygen implantation process takes a long time, which significantly reduces the production yield. Systems obtained by this method also suffer from insufficient quality of the buried silicon oxide layer and of the thin layer of silicon, due to a high density of pinholes.
In this method, the thickness of the silicon layers and the buried silicon oxide layers is determined by the implantation process, namely massive high-dose high-energy oxygen implantation. It is therefore particularly difficult to achieve a thickness of less than 50 nm for the residual silicon layer obtained by this method and less than 80 nm for the buried silicon oxide layer.
A second method, known as the “BESOI technique”, includes forming an SOI system by forming a thin film of SiO
2
on the surface of a first silicon substrate, then uniting the first substrate with a second silicon substrate by means of the thin film of SiO
2
, and finally eliminating a portion of one of the silicon substrates by grinding and mechanically polishing to form a thin layer of silicon on top of the buried silicon oxide layer. The silicon oxide layer on the first silicon substrate is formed by the successive steps of oxidizing the surface of the first substrate and etching the oxide layer formed to obtain the required thickness.
This method can produce only relatively thick buried silicon oxide layers and layers of silicon on the buried silicon oxide layers because of poor control over the etching process. The uniformity of thin layers obtained by this method is poor because of the mechanical steps, which generally cause a raised pattern on the surface of the active layer.
A third method, known as the “SMARTCUT technology” includes forming a thin film of silicon oxide on a first silicon substrate by oxidation, and then implanting H
+
ions in the first silicon substrate under the thin layer of silicon oxide to form a plane of cavities within it. The first substrate is then united with a second silicon substrate by means of the thin layer of silicon oxide. The resulting combination is then subjected to thermal activation for transforming the plane of cavities into a cutting plane.
This method yields an SOI system and a re-usable silicon substrate. It necessitates high-dose implantation of hydrogen atoms. Although hydrogen atoms are small, the surface of the thin layer of silicon obtained is damaged by the formation of pinholes. Also, using this technique does not generally produce a thickness of the thin layer of silicon less than about 50 nm.
In SOI systems obtained in this way the thickness of the active layer of silicon is determined by the hydrogen implantation, enabling cutting of the initial substrate and then final polishing of that layer. The flatness deficiency caused by this method is approximately 5 nm, regardless of the thickness of the final layer. It is therefore a major drawback for a thickness of less than 50 nm. Moreover, for a nominal thickness of less than 50 nm, for example, the variation in thickness from one wafer to another can be on the order of 25% to 40% of the average thickness of a batch of wafers, which forms a major handicap in the production of complex circuits because of the threshold voltage differences resulting from the thickness differences.
The above methods are described in particular in the article “SOI: Materials to Systems”, A. J. Auberton-Hervé, 1996 IEEE.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to provide a method of fabricating an SOI system which remedies the drawbacks of the prior art methods.
This and other objects, advantages and features of the present invention are provided by a method of fabricating an SOI system that produces semiconductor substrates resting on a very thin, highly uniform and highly reproducible layer of an insulative material in the form of thin semiconductor islets surrounded by an insulative material.
According to one aspect of the invention, a method of fabricating, from a first semiconductor substrate having two parallel main surfaces, a system including an islet of a semiconductor material surrounded by an insulative material and resting on another insulative material includes the following steps:
a) producing a layer of a first insulative material intended to surround the semiconductor islet deposited on a top main surface of the first semiconductor substrate;
b) forming on the top main surface of the first semiconductor substrate a thin semiconductor layer forming the islet and which can be selectively etched relative to the first semiconductor substrate;
c) forming a layer of a second insulative material on the surface formed by the islet of the first insulative material and the thin semiconductor layer; and
d) removing the first semiconductor substrate.
In the context of the invention the expression “main surfaces”, when referring to a semiconductor substrate, means the largest surfaces of the substrate that are subjected to the various steps of the method, as opposed to its lateral surfaces.
According to another aspect of the invention, a bottom main surface of the first semiconductor substrate rests on a top main surface of a second semiconductor substrate which can be selectively etched relative to the first semiconductor substrate. Adding a second semiconductor substrate under the first semiconductor substrate reduces the cost of fabricating a system in accordance with the invention by red
Jaouen Herve
Le Goascoz Vincent
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Coleman William David
STMicroelectronics SA
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