Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-12-19
2002-07-09
Ghyka, Alexander G. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000
Reexamination Certificate
active
06417033
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a silicon island in semiconductor substrate. More particularly, the invention provides a method of fabricating a silicon island of mono-crystalline silicon for making electronic devices.
2. Description of the Related Art
Since Silicon-On-Insulator (SOI) devices are fabricated on a thin silicon film on a insulator, the parasitic capacitance of the source/drain of MOSFET to the substrate below is greatly reduced and the operation speed is substantially improved compared to conventional microelectronic circuit fabrication on bulk silicon substrate (Bulk Devices). Thus SOI have tremendous advantage for very large scale integration (VLSI) of electronic devices over conventional Bulk Devices. In SOI fabrication, the channel length of the source/drain is reduced thereby decreasing the area and effectively increasing the integration of a semiconductor device. Additionally, device isolation of the SOI devices can be easily achieved with shallow trench isolation (STI) techniques by simply etching off unnecessary parts of silicon film surrounding areas to be used for SOI devices.
However, SOI devices are difficult to fabricate and expensive. Additionally, SOI devices have inherent drawbacks due to build-up of hot carrier generated during the operation. During SOI operation, from time to time, a high electric field concentrates around the drain region. Electric charges flowing in the channel are accelerated by the strong electric field around the drain and generates the opposite electric carriers by impact ionization which then flows back to the body of the device. Since SOI is completely isolated electrically from the substrate below, the created carriers cannot be drained into the substrate and thus builds up in the body of the SOI, this causes floating body effect, i.e. a shift of electrical potential in the body of SOI device with carrier build up. This floating body effects then induces undesirable transition in device performance such as change of threshold voltage with time.
Therefore, holes are confined inside the SOI device body. When a forward voltage is applied between the source and the body, holes in the body start to flow out of the source forming parasitic bipolar action path. With this new electron path formed away from gate electrode besides proper channel current path at the interface between silicon and gate oxide, the SOI device shows unexpected irregular operation so called kink effect.
Further, formation of electrical pathways through the insulating material requires process steps to open a small hole through the insulating region whose dimensions become less than 0.25 mm in the deep sub-micron device era (if the hole is larger compared with the insulating region, the device loses advantages of SOI device). Formation of such small holes precisely aligned within the insulating region whose dimensions are less than 0.25 mm is extremely difficult and almost impractical as a ULSI manufacturing method. Furthermore, the method requires a crystallization step even for constructing a single level planar circuit, which is inefficient, when a single crystal level is already available on the original substrate surface.
Therefore, improved devices structure and a simple fabrication which realize high speed operation as with conventional SOI devices but without any adverse effects related to the charge build-up is highly desired. In order to overcome the above defects a thin-foot charge drain beneath the conventional SOI structure to sweep out undesirable charge build-up generated by hot carrier effects during device operation desirable.
Referring to
FIG. 1A
, is a schematic diagram illustrating a conventional SOI, a silicon nitride film
102
about 2000 A thick is formed on a silicon substrate
100
using a CVD technique, a photoresist mask
104
is formed.
Next, referring to
FIG. 1B
, a reactive ion etching (RIE) is performed to penetrate etching through silicon nitride layer
102
and the underlying silicon substrate
100
, forming a trench
105
forming a silicon island structure
112
. During the etching process, a thin passivation layers
106
are formed on the sidewall of the trench
105
.
Next, referring to
FIG. 1C
, an anisotropic (chemical) dry etching using CF
4
/
02
plasma is performed. The passivation layers
106
forms a protective layer on the sidewalls and is unaffected by etching. While the horizontal bottom surface has no passivation layers are etched eroding the bottom surface and forming a foot of a silicon island
110
as shown.
However, there is a problem in fabricating a silicon island with a thin foot region under the island using the method as described above. It is very difficult to control the etching process for obtaining a desired foot thickness in a deep submicron device, often over-etching and breaking off of the structure
112
occurs.
SUMMARY OF THE INVENTION
The present invention provides an improved method of fabricating a thin-foot region underneath the SOI structure. In the method it is very easy to control the oxidation process for obtaining a desired foot thickness in a deep submicron device. The drawbacks of the conventional etching step, such as over-etching and breaking off of the island structure will not occur in the invention. The thin foot region is easily formed by controlling conditions of oxidation, such as time or temperature of oxidation.
The invention provides a method of manufacturing a semiconductor device comprising the following steps. A silicon substrate is provided. A first oxidation-resistant layer is formed on the silicon substrate. The first oxidation-resistant layer and the silicon substrate are formed to form a trench. A second oxidation-resistant layer if formed on the first oxidation-resistant layer and inside the trench. A portion of the second oxidation-resistant layer is removed to form a spacer on sidewalls of the trench. A portion of the exposed silicon substrate on bottom of the trench is performed by directional etching to expose a portion of the sidewalls of the trench. A thermal oxidation step is performed on the exposed portion of the sidewall of the trench. The second spacer is removed and a dielectric layer is formed over the substrate to fill in the trench.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5039621 (1991-08-01), Pollack
patent: 5691230 (1997-11-01), Forbes
patent: 5963789 (1999-10-01), Tsuchiaki
patent: 6015725 (2000-01-01), Hirayama
patent: 6174784 (2001-01-01), Forbes
patent: 6211039 (2001-04-01), Noble
patent: 6319333 (2001-11-01), Noble
Ghyka Alexander G.
J.C. Patents
Vanguard International Semiconductor Corp.
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