Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-05-18
2002-01-29
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S532000, C438S533000, C438S715000, C438S717000, C438S719000, C438S721000
Reexamination Certificate
active
06342452
ABSTRACT:
FIELD OF INVENTION
The present invention relates to the manufacture of semiconductor integrated circuits and more particularly to an improved method of forming a composite Si3N4/polycide structure laterally coated with a Si3N4 spacer that has a low aspect ratio. Typically, such a composite structure consists of a top silicon nitride (Si3N4) layer, an intermediate refractory metal silicide layer (e.g. WSix) and a bottom doped polycrystalline silicon (polysilicon) layer. The deposition of a refractory metal silicide over a layer of doped polysilicon is extensively used in the semiconductor industry, forming a so-called polycide layer. The above method finds a valuable application in the fabrication of borderless metal contacts.
BACKGROUND OF THE INVENTION
In the manufacture of such advanced semiconductor IC's, particularly in dynamic random access memory (DRAM) chips, insulated gate field effect transistors (IGFETs) are extensively used. In a particular implementation commonly found in 16/64 Mbit DRAM chips, each individual memory cell is comprised of an IGFET and a storage capacitor. A composite Si3N4/polycide structure can be found above a silicon substrate coated with a thin SiO2 gate layer to form the gate conductor of the IGFET as known for those skilled in the art. The gate conductor formation which requires the step of etching such a Si3N4 dielectric/polycide structure is essential in the fabrication of the borderless metal contact with a diffusion (source/drain) region of the IGFETs. The borderless metal contact fabrication will be now briefly described by reference to
FIGS. 1A-1F
.
FIG. 1A
schematically shows a portion of a semiconductor wafer at the initial stage of the borderless metal contact fabrication. In
FIG. 1A
, there is shown a conventional semiconductor structure
10
comprising a silicon substrate
11
coated by a thin 8.5 nm silicon oxide (SiO2) layer
12
(the gate dielectric of the IGFETs) with the gate conductor (GC) stack
13
formed thereon. The GC stack
13
typically consists of a plurality of layers that are superposed: a bottom 150 nm thick arsenic doped polysilicon layer
14
, an intermediate 120 nm thick tungsten silicide (WSix) layer
15
, and a 410 nm thick silicon nitride (Si3N4) capping layer
16
. The Si3N4 capping layer
16
and the combined WSix/doped polysilicon materials of layers
15
and
14
thus form the dielectric/polycide structure mentioned above. Finally, a bottom anti-reflective layer, referred to hereafter as the BARL layer
17
and a photoresist layer
18
terminate the layered structure shown in FIG.
1
A. The BARL layer
17
thickness is typically of about 90 nm. As apparent in
FIG. 1A
, the thickness of stacked layers
14
to
17
is represented by parameter A′.
The GC stack
13
delineation process starts with the patterning of the photoresist layer
18
to produce the desired mask which will subsequently be used to transfer the desired pattern fixed in the resist mask to the underlying layers. To that end, the photoresist layer
18
is exposed, baked and developed as standard. The BARL and the Si3N4 materials of layers
17
and
16
are dry etched in sequence in the same tool. A CF4/CHF3/02/Ar chemistry and an AME P5000 RIE etcher manufactured by Applied Materials, Santa Clara, Calif., USA are adequate for that step. The etch process is monitored through an optical etch end point system as standard.
The etch operating conditions are:
Ar flow
16
sccm
CF4 flow
120
sccm
CHF3 flow
45
sccm
O2 flow
7.5
sccm
Pressure
160
mTorr
RF freguency
13.56
Mhz
Bias power
870
Watt
Magnetic Field
30
Gauss
Duration
50
s (BARL)
110
s (Si3N4)
wherein “sccm” denotes standard cubic centimeters per minute.
The resulting structure is shown in FIG.
1
B. Now turning to
FIG. 1B
, the dimensions of GC stacks and spaces therebetween is represented by C
1
and B
1
respectively. The dimensions of C
1
and B
1
are derived from the dimensions C″ and B″ of the physical mask used for the resist layer
18
exposition. As further apparent in
FIG. 1B
, the resist layer
18
lateral profile exhibits typical dimensional swings forming the undulations depicted therein. This defect induces polymer residues on the BARL layer
17
sidewall, which in turn creates a “foot” at the base of Si3N4 layer
16
.
Now, the BARL layer
17
and the photoresist mask
18
are stripped by ashing in ozone and structure
10
is cleaned as standard.
The next step consists in transferring the pattern into the underlying WSix layer
15
using the remaining part of the Si3N4 capping layer
16
, referred to hereinbelow as the Si3N4 cap
16
, as an in-situ hard mask. This step is monitored by an optical etch end point system to detect the WSix layer
15
/doped polysilicon layer
14
interface. This process uses a C12/HC1/O2 chemistry with a LAM TCP 9400 plasma etcher, an equipment sold by LAM RESEARCH Corp., Fremont, Calif., USA.
The operating conditions are:
C12 flow
60 sccm
HCL flow
120 sccm
O2 flow
8 sccm
Pressure
5 mTorr
RF frequency
13.56 Mhz
TCP power
400 Watt
Bias power
105 Watt
Next, the doped polysilicon layer
14
is etched in the same RIE etcher without stopping plasma discharge. The mixture is now reduced to the C12 and O2 compounds. This composition change aims to increase selectivity between doped polysilicon and SiO2 in order to preserve SiO2 gate layer
12
integrity. The etch operating conditions becomes:
C12 flow
20
sccm
O2 flow
3
sccm
He flow
100
sccm
Pressure
15
mTorr
RF frequency
13.56
Mhz
TCP power
200
Watt
Bias power
35
Watt
This step is monitored by an optical etch end point system to detect the doped polysilicon layer
14
/SiO2 layer
12
interface.
An overetch is performed during a fixed time (60 seconds) in order to eliminate polysilicon residuals without affecting the integrity of the SiO2 material of the thin gate dielectric layer
12
. At this stage of the fabrication process, the structure
10
is shown in FIG.
1
C. Because the chemistry used to etch the WSix layer
15
is very aggressive, a non negligible part of the Si3N4 cap
16
is consumed during this step. This erosion which is visible in
FIG. 1C
, reduces the GC stack
13
height which is indicated by reference A
1
in FIG.
1
C. The wafer is cleaned in a DHF solution as standard to remove the SiOx residuals formed on the SiO2 gate layer
12
and on the GC stack sidewall during the previous etch step in order to adjust the profile topography. As apparent in FIG.
1
C. the remaining portions of the GC stack now have the general shape of lines, but are still indicated by reference numeral
13
.
The borderless contact to diffusion fabrication process continues with the formation of Si3N4 spacers coating the lateral sides of the GC stacks
13
for sidewall protection. The material deposited has the same nature as the Si3N4 used for capping the GC stacks
13
. To that end, a 60 nm thick Si3N4 layer is conformally deposited by low pressure chemical vapor deposition (LPCVD) onto the structure
10
and anisotropically etched in an RIE reactor to form Si3N4 spacers referenced
19
in FIG.
1
D. An optical etch end point system is used to detect the SiO2 gate layer
12
exposure as standard. A diffusion (source/drain) region
20
of the IGFET is then formed by ion implantation in desired locations as standard. At this stage of the GC stack fabrication process, the structure is shown in FIG.
1
D.
Still referring to
FIG. 1D
, the Ap parameter which measures the GC stack
13
height is obtained after a succession of processing steps. As a matter of fact, the GC stack initial height A′ is reduced to a value A
1
after the WSix layer
15
etching which has caused a significant consumption of the material of Si3N4 cap
16
(due to the use of a non-selective chemistry) and then further reduced to a value Ap because of the overetch of Si3N4 spacer
19
. Now, if we consider the Bp parameter which is the width between two GC stacks
13
coated with the Si3N4 spacer
19
, it is very dependent on the thickness of spacer
19
and the overetch. Parameter Bp is first determined by para
Coronel Philippe
Costaganna Pascal
Heineck Lars
C. Li Todd M.
International Business Machines - Corporation
Neff Daryl K.
Tran Binh X.
Utech Benjamin L.
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