Method of fabricating a semiconductor memory device

Details Method of fabricating a semiconductor memory device Method of fabricating a semiconductor memory device

2002-05-31

2004-04-20

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S275000, C438S278000, C438S525000, C438S705000

Reexamination Certificate

active

06723649

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a method of fabricating a mask read-only memory (ROM).
2. Description of the Related Art
Mask ROM (Read Only Memory) is one of the non-volatile memories that retain data even when electric power is off. The MOS transistor array in mask ROM is defined by a photomask during fabrication and the data is programmed according to the photomask pattern. After the data is written in mask ROM, it is neither erasable nor programmable, which makes mask ROM a high capacity, high reliability and low cost memory device applied in various kinds of information, communication or consumption products to store critical data.
Mask ROM can be classified into NAND-type ROM and NOR-type ROM. It is considered that NOR-type ROM is superior in terms of operation speed. A conventional method of NOR-type ROM fabrication is disclosed in U.S. Pat. No. 5,911,106 by Tasaka Kazuhiro. The fabrication process of a NOR-type mask ROM is shown on FIG.
1
and
FIGS. 2A
to
2
D.
FIG. 1
is the top view of an array configuration of memory cells of the NOR-type mask ROM. Bit lines
6
of diffusion regions of an N conductivity type formed in a silicon substrate of a P conductivity type extend in a vertical direction, and word lines
8
are disposed above and extend orthogonal to the direction of the bit lines
6
. The word lines
8
are made of a polycide structure that is a laminate structure of a lower polycrystalline silicon layer and an upper slicide layer. Below each of the word lines
8
and between the adjacent two bit lines
6
is formed a channel of a memory cell transistor.
FIGS. 2A
to
2
D show the fabrication process of the flat NOR-type mask ROM. In
FIG. 2A
, the surface of a silicon substrate
1
of P conductivity type is subjected to oxidation to grow oxides to form a pad oxide film
2
and a silicon nitride film
3
is deposited on the film
2
. The silicon nitride film
3
acts as an oxidation resisting film. A resist (photoresist)
4
is formed on the silicon nitride film
3
. The resist
4
has openings where diffusion regions of N conductivity, which act as bit lines, are to extend.
The silicon nitride film
3
is selectively removed, as shown in
FIG. 2B
, by anisotropic etching technique with the resist
4
as a mask. Using the resist
4
as a mask, ion implantation is performed vertically, which means the implantation angle is 0°, to introduce dopants of N conductivity type, such as arsenic (As), into the substrate
1
to form N-type dopant implanted portions below the openings.
In
FIG. 2C
, still using the resist
4
as a mask, ion implantation is performed vertically with the implantation angle 0° to introduce dopants of P conductivity type, such as boron (B), into the substrate
1
to form P-type dopant implanted portions below the openings. The implantation energy of P-type ions is greater than the N-type ion implantation, and therefore the P-type dopant implanted portions are formed right below the N-type dopant implanted portions.
In
FIG. 2D
, after the resist
4
has been removed, selective oxidation is performed with the silicon nitride film
3
as a mask. In the selective oxidation, the implanted dopant atoms are diffused to form dopant diffusion regions
6
of N conductivity and regions
10
of P conductivity and field oxide regions
5
are formed on the dopant diffusion regions
6
. These dopant diffusion regions
6
act as bit lines.
In
FIG. 2E
, after removing the silicon nitride film
3
and pad oxide film
2
to expose surface portions of the silicon substrate
1
, gate oxide regions
7
are formed on the exposed surface portions of the silicon substrate
1
. Subsequently, a laminated structure of a lower polycrystalline silicon film and an upper tungsten silicide (WSi) film are deposited over the whole surface of the assembly, and patterned to define word lines
8
. Formed below each of the word lines
8
and between the adjacent two of the N conductivity-type diffusion regions
6
(bit lines) is a channel
9
.
In the conventional fabrication process describing above, the silicon nitride film
3
is formed as a mask of oxidation to prevent the active areas defined in the silicon substrate
1
from being oxidized. Therefore, an additional step is needed to remove the silicon nitride film
3
after oxidation.
Moreover, in the conventional fabrication process described above, the field oxide
5
is first formed with the silicon nitride film
3
as a mask during oxidation. After the field oxide
5
is formed, the silicon nitride film
3
is then removed, and the gate oxide
7
is formed by another oxidation subsequently. It takes at least three steps to complete the fabrication of field oxide
5
and gate oxide
7
.
SUMMARY OF THE INVENTION
To simplify the fabrication of mask ROMs, one object of the present invention is to provide a method for fabricating a mask ROM without a silicon nitride film as a mask.
Another object of the present invention is to provide a method for fabricating a mask ROM which provides a pad oxide film or a pad oxide/bottom anti-reflection layer as a mask during oxidation to reduce the number of fabrication steps.
To achieve the above-mentioned objects, a method for fabricating a semiconductor memory device, such as a mask ROM, comprises the following steps.
First, a sacrificial oxide layer is formed on a semiconductor substrate and then a photoresist layer is formed on the sacrificial oxide layer. Second, the photoresist layer is patterned to form a plurality of openings where bit lines are to extend respectively. Taking the patterned photoresist layer as a mask, first type ions are implanted into the semiconductor substrate through the openings and then second type ions are implanted into the semiconductor substrate through the openings. The first type ions and the second type ions are electrically opposite and the implantation depth of the second type ions are deeper than the first type ions. The photoresist layer and the sacrificial oxide layer are removed after implantation. A gate oxide and a field oxide are grown simultaneously on the non-implanted and the implanted regions of the semiconductor layers respectively and a gate conductive layer is deposited on the semiconductor substrate.
Further, in a preferred embodiment, a bottom anti-reflective coating (BARC) is deposited between the sacrificial oxide layer and the photoresist layer to reduce multiple reflection and interference in photo-lithography. The sacrificial oxide layer can be silicon oxide as a pad oxide. The first type ions can be N-type, such as arsenic ion (As
+
), and the second type ions can be P-type, such as boron (B). The second type ions can be implanted at a 0 degree (0°) angle or implanted at an angle greater than 0°, which means a pocket implantation, into the semiconductor substrate. The gate conductive layer can be a poly-silicon material.
According to the invention, the fabrication process of a mask ROM is simplified and there is no need to form a silicon nitride layer as a mask. Therefore, the step of removing silicon nitride layer is not required. Moreover, the gate oxide and the field oxide are formed simultaneously in an oxidation process according to the present invention. The advantage of the method of fabricating a mask ROM in the invention is simplifying the fabrication process and therefore reduces the cost of fabrication and fabrication time.


REFERENCES:
patent: 6077746 (2000-06-01), You et al.
patent: 6248635 (2001-06-01), Foote et al.

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