Fishing – trapping – and vermin destroying
Patent
1995-08-07
1997-09-23
Chaudhari, Chandra
Fishing, trapping, and vermin destroying
437195, 437228PL, H01L 218242
Patent
active
056704097
ABSTRACT:
A method of fabricating a semiconductor integrated circuit device includes: recessing a second surface portion of a semiconductor substrate; forming elements of a first circuit region capable of performing a first function at a first surface portion of the semiconductor substrate and elements of a second circuit region capable of performing a second function at the recessed second surface portion of the semiconductor substrate, the elements of the first circuit region and those of the second circuit region having relatively small and large sizes as generally measured in a direction perpendicular to the surface portions of the semiconductor substrate, respectively; forming an insulating film to cover the first and second circuit regions, with a result that a level difference is caused between first and second portions of the insulating film on the first and second circuit regions at a relatively lower level and at a relatively higher level, respectively; effecting chemical-mechanical planarization of the insulating film to suppress the level difference in the insulating film for enhancing a focus margin for successive photolithographic steps; and forming wiring conductors on the insulating film with the suppressed level difference, enjoying the enhanced focus margin.
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Kajigaya Kazuhiko
Kanai Fumiyuki
Koike Atsuyoshi
Kubo Masaharu
Miyazawa Kazuyuki
Chaudhari Chandra
Hitachi , Ltd.
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