Method of fabricating a semiconductor device using two...

Details Method of fabricating a semiconductor device using two... Method of fabricating a semiconductor device using two...

2002-03-12

2004-04-20

Fahmy, Wael M. (Department: 2814)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S745000, C438S749000, C438S759000

Reexamination Certificate

active

06723644

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to the process of planarizing a surface on a semiconductor substrate in the fabricating of a semiconductor device.
2. Description of the Related Art
A semiconductor integrated circuit chip is a micro electronic device made up of various semiconductor devices integrated on a semiconductor substrate. As semiconductor devices become more highly integrated and more compact, and as the number of wiring layers of the semiconductor devices increase, step differences at the various surfaces on the substrate increase. A variety of techniques for planarizing these surfaces to eliminate the step differences have been developed. These planarizing techniques include silicon-on-glass (SOG), etch-back, reflow, and chemical mechanical polishing (CMP) techniques.
In particular, CMP is one of many very large scale integrated (VLSI) processing techniques and is considered to be a core technique for achieving high degrees of integration in semiconductor devices. Specifically, CMP is a global planarization technique for chemically and mechanically planarizing a surface to remove irregularities at the surface. In CMP, a polishing pad is pressed against a wafer surface on which particular material layers are formed, a polishing liquid, such as a slurry, is fed between the wafer surface and the polishing pad, and the polishing pad and the wafer are rotated in opposite directions.
The density of patterns formed on a wafer can considerably affect the subsequent deposition of layers and the CMP performed on deposited layers.
FIGS. 1 and 2
are cross-sectional views illustrating the effects of the density of patterns on subsequent processes.
Referring to
FIG. 1
, a plurality of conductive patterns, which consist of a conductive layer
12
and a first stopper layer
14
, are formed on a semiconductor substrate
10
. Note,
FIG. 1
illustrates only part of a semiconductor wafer. In
FIG. 1
, the region marked “A” is a cell region and the region marked “B” is a peripheral region. As shown in
FIG. 1
, complex semiconductor devices are formed in the cell region A, whereby the density of patterns in the cell region A is very high. On the other hand, alignment key patterns or some resistant layers are formed in the peripheral region B and thus, the density of patterns in the peripheral region B is low.
An interlayer insulating layer
16
for forming a multi-layered structure is deposited on the resultant substrate
10
. The interlayer insulating layer
16
is thicker at the cell region A, which has a higher pattern density, than at the peripheral region B, which has a lower pattern density.
FIG. 2
shows dishing occurring after CMP is performed on the interlayer insulating layer
16
. Because CMP is a global planarization technique, a predetermined thickness of the interlayer insulating layer
16
is removed along the entire wafer until the first stopper layer
14
in the peripheral region B is exposed. In this case, the entire surface of the interlayer insulating layer
16
does not become entirely flat, i.e., dishing occurs at the peripheral region B. If the CMP were performed further, the first stopper layer
14
would become too thin or the conductive layer
12
under the first stopper layer
14
would be exposed. In
FIG. 2
, the step difference between the cell region A and the peripheral region B is exaggerated so that the dishing that occurs in the prior art can seen more easily.
As described above, the peripheral region B is chemically and mechanically polished more than the cell region A. The reasons for this are as follows. First, the surface height of the interlayer insulating layer
16
becomes greater at the cell region A than at the peripheral region B as a result of the deposition process, because the cell region A has a greater pattern density than the peripheral region B. Secondly, even though a particular amount of slurry is fed between the semiconductor substrate
10
and the polishing pad (not shown), more slurry feeds to the peripheral region B than to the cell region A due to the difference in pattern density between the cell region A and the peripheral region B.
Dishing may cause the conductive layer
12
to be damaged by a subsequent cleaning process. In addition, in a case in which another conductive layer is subsequently formed on the interlayer insulating layer
16
, such a conductive layer may be short-circuited at the peripheral region B.
FIG. 3
shows a fabrication technique of the prior art for solving the above-described dishing problem. Referring to
FIG. 3
, dummy patterns are formed in the peripheral region B to increase the pattern density of the peripheral region B. As a result, the height of the interlayer insulating layer
16
is relatively uniform along the entire. Thus, the entire surface on the substrate
10
will become flat when CMP is performed.
However, some semiconductor integrated circuit designs make it impossible to form dummy patterns in a region intended to have a lower pattern density. For instance, it may be impractical to use dummy patterns in consideration of the characteristics of processes subsequent to the formation of the interlayer insulating layer
16
or the characteristics of the semiconductor device to be formed. In addition, unexpected parasitic capacitance may occur between the conductive layers of each of the dummy patterns, thereby creating operation failures in the semiconductor device.
SUMMARY OF THE INVENTION
It is thus an object of the present invention to overcome the above-described problems of the prior art.
More specifically, it is a first object of the present invention to provide a method of manufacturing a semiconductor device that is capable of preventing a dishing phenomenon from occurring as the result of chemical mechanical polishing, and which method does not involve the use of dummy patterns.
It is a second object of the present invention to provide a method of manufacturing a semiconductor device in which chemical mechanical polishing is effectively carried out on regions of the same semiconductor substrate having significantly different pattern densities.
To achieve these objects, the method of manufacturing a semiconductor device according to the present invention uses a second stopper layer formed on the interlayer insulating layer, and two polishing processes. An etching mask is formed on the second stopper layer so as to discriminate a first region having a high conductive pattern density from a region(s) having a low pattern density. Using the etching mask, the second stopper layer and part of the interlayer insulating layer are etched at the first region. Next, a first polishing process is performed, using a slurry providing a polishing rate that is higher for the interlayer insulating layer than for either the first and second stopper layers, to expose the surface of the first stopper layer. Finally, a second polishing process is performed, using a slurry providing a polishing rate that is higher for the second stopper layer than for either the first stopper layer and the interlayer insulating layer, to remove the second stopper layer from the region(s) having the lower pattern density.
The present invention is particularly applicable to a semiconductor substrate divided into a cell region having a high conductive pattern density and a peripheral region having a low conductive pattern density.
Preferably, the first stopper layer is a silicon nitride layer, the interlayer insulating layer is an oxide layer, and the second stopper layer is a polysilicon layer.
Preferably, the first polishing process polishes the interlayer insulating layer at rate that is 4-500 times greater than that at which either of the first and second stopper layers is polished. Similarly, the second polishing process preferably polishes the polysilicon layer at a rate that is 4-500 times greater than that at which either the first stopper layer and the interlay

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