Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-10-12
2003-09-23
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S639000, C438S645000, C438S648000, C438S688000, C438S722000, C438S723000, C438S724000, C438S259000, C257S330000
Reexamination Certificate
active
06624065
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device using a damascene metal gate enabling the prevention of electric short circuits.
2. Description of the Related Art
Polysilicon or polycide gate electrodes are used for sub-0.1 &mgr;m devices in general. Yet, use of a polysilicon gate results in a number of unintended consequences, such as increasing effective thickness of gate insulating layers due to gate depletion effect, threshold voltage variance due to boron penetration from a p+ or n+ doped polysilicon gate into a substrate, dopant distribution fluctuation and the like. Moreover, an inability to maintain low resistance has been noted in devices having submicron CD having gates using polysilicon.
Therefore, continued decrease in the size of gate electrodes below submicron size requires developments for new materials and structures as substitutes for the conventional gates using polysilicon.
In order to meet such requirements, many efforts have been made to develop metal gate electrodes. Certain disadvantages and problems, such as boron penetration and gate depletion, do not arise in a metal gate using no dopant. Moreover, the metal gate has a work function value that corresponds to a mid-band gap of silicon, thereby allowing application to a single gate enabling the formation of a symmetric threshold voltage in NMOS and PMOS areas. In this case, W, WN, Ti, TiN, Mo, Ta, TaN and the like are metals for which work function values correspond to the mid-gap of silicon.
A transistor using a metal gate electrode, when fabricated by a conventional method using a polysilicon gate electrode, gives rise to fatal defects, such as a difficulty in patterning a metal gate electrode, generation of plasma damage caused by plasma produced by ion implantation for forming the source/drain regions, and thermal damage due to thermal treatment after ion implantation.
A new metal gate damascene process for forming a metal gate electrode is described to overcome these disadvantages resulting from use of metal gates in a semiconductor device.
The metal gate damascene process for forming a metal gate electrode includes the steps of forming a polysilicon gate as a dummy gate, forming source/drain regions so as to complete a transistor, removing the polysilicon gate as the dummy gate, and forming a metal gate using a damascene process.
A method of fabricating a semiconductor device using a damascene metal gate according to a related art is explained by referring to
FIGS. 1
to
7
, as follows.
FIGS. 1
to
7
illustrate cross-sectional views of a semiconductor device showing the fabrication steps using a method of forming a damascene metal gate according to a related art.
Referring to
FIG. 1
, a silicon oxide layer and a polysilicon layer are formed on a silicon substrate
11
by a conventional method of forming a polysilicon gate electrode. A dummy gate insulating layer
12
and a dummy gate electrode
13
are then formed by patterning the polysilicon and silicon oxide layers, respectively.
Subsequently, spacers
14
are formed at both sidewalls of the dummy gate insulating layer
12
and the dummy gate electrode
13
.
Source/drain regions (not shown) are formed in the semiconductor substrate
11
below both lateral sides of the spacers
14
by ion implantation.
Referring to FIG.
2
and
FIG. 3
, an insulating interlayer
15
is formed on an entire surface of the substrate
11
. The dummy gate electrode
13
is then exposed by polishing the insulating interlayer
15
by chemical mechanical polishing (CMP).
Referring to
FIG. 4
, a trench
16
is formed by selectively etching the exposed dummy gate electrode
13
and the exposed dummy gate insulating layer
12
underneath so as to expose the substrate
11
where the dummy gate electrode
13
and dummy gate insulating layer
12
have been removed.
Referring to
FIG. 5
, an insulating layer
17
and a metal layer
18
are formed on the insulating interlayer
15
including on the trench
16
.
Subsequently, the insulating interlayer
15
is exposed by selectively removing the insulating layer
17
and metal layer
18
by polishing or other appropriate method. A damascene gate insulating layer
19
and a damascene metal gate electrode
20
are formed, the damascene gate insulating layer
19
being formed of a general gate insulator such as silicon oxide, Ta
2
O
5
, Al
2
O
3
or the like, and the damascene metal gate electrode
20
being formed of tungsten. Alternatively, the damascene metal gate electrode
20
may be formed of a material taken form a group comprising one or more of the following metals or alloys: WN, Ti, TiN, Ma, Ta and the like.
Referring to
FIG. 7
, an insulating interlayer
21
is formed on an entire surface of the substrate
11
. Contact holes
23
, such as a bitline contact hole or a storage electrode contact hole, are then formed by etching the insulating interlayer
21
using a photoresist layer
22
as a mask so as to expose the source/drain regions (not shown). Metal wires or bitline/storage electrode wire for a memory device, not shown in the drawing, provide electrical connections to the source/drain regions (not shown) through the contact holes
23
.
The above-explained conventional method of fabricating a semiconductor device using the damascene metal gate electrode has certain disadvantages. In the related art, the damascene metal gate electrode is formed after the formation of the source/drain regions, thereby inhibiting plasma damage caused by the ion implantation for source/drain and the thermal damage caused by the succeeding thermal treatment, both of which are encountered in the conventional method of forming a damascene metal gate electrode.
Unfortunately, non-uniformity in the contact exposure process occurs in the conventional method of fabricating a semiconductor device, especially when the device is more highly integrated, whereby the damascene gate electrode is exposed as shown in FIG.
7
.
Therefore, as shown at ‘A’ in
FIG. 7
, the damascene gate electrode is exposed due to non-uniformity in the contact exposure process, thereby resulting in an undesirable short-circuit with a bitline or a storage electrode line formed in a succeeding process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a semiconductor device using a damascene metal gate that substantially avoids one or more of the problems resulting from the above-described limitations and disadvantages of the related art.
The object of the present invention is to provide a method of fabricating a semiconductor device using a damascene metal gate so as to prevent a short-circuit caused by non-uniformity in the contact exposure process.
Additional features and advantages of the invention will be set forth in the detailed description of preferred embodiments, which follows, and in part will be apparent from that description or study of the drawing figures, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as in the appended drawings.
To achieve these and other advantages, and in accordance with the purposes of the present invention as embodied and broadly described herein, a method of fabricating a semiconductor device using a damascene metal gate according to the present invention includes the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate electrode by selectively etching a portion of the damascene gate electrode to a predetermined thickness, forming an insulating layer in the trench at the upper part of the damascene gate electrode, forming an insulating interlayer on an upper surface of the entire structure, and forming a contact hole expo
Cheong Woo Seock
Jang Se Aug
Hynix / Semiconductor Inc.
Keshavan B V
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