Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2006-10-09
2008-03-04
Nguyen, Thanh T. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
C438S366000, C438S368000, C438S369000, C257SE27030
Reexamination Certificate
active
07338875
ABSTRACT:
Formation of elements of a vertical bipolar transistor is described, in particular a vertical npn transistor formed on a p-type substrate. Accordingly, an improved method not limited by constraints of photolithography, and an ensuing device made by such methods, is described. A temporary spacer (e.g., an oxide spacer) is deposited over a dielectric separation layer. The temporary spacer and dielectric separation layers are then anisotropically etched, forming a dielectric “boot shape” on a lower edge of the dielectric separation layer. An area within this non-photolithographically produced boot region defines an emitter contact window. Since the boot tip is formed through deposition and etching techniques, the emitter window is automatically aligned (i.e., self-aligned) with an underlying base region. Feature sizes are determined by deposition and etching techniques. Consequently, photolithography of small features is eliminated.
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patent: 5512785 (1996-04-01), Haver et al.
Wolf et al. “Silicon Processing for the VLSI Era” 1986, vol. 1, pp. 521-523.
Atmel Corporation
Nguyen Thanh T.
Schneck Thomas
Schneck & Schneck
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