Method of fabricating a semiconductor device

Details Method of fabricating a semiconductor device Method of fabricating a semiconductor device

2002-02-15

2004-11-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S639000, C438S643000, C438S653000, C438S700000

Reexamination Certificate

active

06821884

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to Integrated Circuit (IC) processing and fabrication. A device and a method are provided for etching an opening in an insulating layer while depositing a barrier layer on the side walls of the opening without essentially depositing a barrier layer on the bottom of the opening.
BACKGROUND OF THE INVENTION
Over the years, the demand for higher speed integrated circuits has been addressed through shrinkage of the device dimensions and increase of the packing density of the devices in integrated circuits or on carrier packages. By decreasing the layout rules of the devices, one can obtain transistors with higher intrinsic switching speed. In addition, putting the devices closer to each other reduces the communication time between transistor devices. Both approaches allow building circuits with increased overall performance, i.e., higher switching speed combined with higher functional circuits. Additionally, the integrated circuit area has increased, leading to circuits with even higher functionality as more devices can be integrated in a given area.
The structures connecting these devices can comprise multiple metal levels which are, depending upon the aimed interconnect pattern, either separated one from another by means of interlevel electrically insulating layers or connected one to the other by means of a conductive connection through these insulating layers. These insulating layers also take part in the separation of interconnect structures defined on the same metal level. Besides the downscaling of the dimensions of these interconnecting structures, additional measures are required to be able to meet the stringent speed specifications.
For future technologies the increasing impact of the back end processing in the fabrication of integrated circuits is recognized. A major change in back end processing is necessitated by the ever-decreasing feature size of the devices of integrated circuits that has indicated RC delay-time of the interconnect structures to be the limiting speed factor of the next generation of integrated circuits. To address this problem, two major routes are being explored: introduction of metals with higher conductivity and introduction of dielectric materials with lower dielectric constants.
The introduction of these materials has changed the outlook of the back end processing schemes where dry etch processes, cleaning recipes, and barrier requirements all need to be adapted.
Although aluminum alloys and oxides are still widely used in interconnect technology, copper and new low-k dielectrics, e.g., polymers, are rapidly being implemented in microelectronics as they are now accepted as the future materials of choice. Copper offers a lower resistance and, depending on many processing parameters, this low resistivity can be combined with a better resistance to electromigration. The introduction of copper requires the introduction of damascene processing, which is an important change with respect to classical processing that uses patterning of the conductive elements. In damascene processing, trenches are formed in the insulating layers. After the patterning of the trenches, metal layers are deposited in the trenches and on top of the insulation layers. Finally, the metal layer is polished down to the top of the insulating layers, leaving only the via and trenches filled with metal.
The use of copper in interconnect structures has some commonly known disadvantages. Copper can diffuse very fast in the surrounding insulating layers, such as the low-k materials, which negatively affects the reliability and the signal delay. Several solutions have been proposed to solve this problem. The currently used techniques inhibit the migration of copper ions in the surrounding layers by depositing, in a non-selective way, diffusion barrier layers, e.g., refractory metals such as tantalum nitride (TaN), titanium nitride (TiN) in between the copper and the insulating layers. The horizontal, i.e. the bottom, as well as the vertical side walls of an opening in these insulating layers, e.g. a via or contact hole, are therefore covered with a barrier material. In case of Chemical Vapor Deposition (CVD) techniques, the barrier is conformal deposited. In case of Physical Vapor Deposition (PVD) techniques, the coverage of the vertical side walls of an opening and the bottom of this opening is less, compared to the coverage of the top of the opening. However, the ratio between side wall and horizontal coverage can be tuned to a certain extent by modifying the process parameters, such as deposition power and the bias of deposition.
Several problems are related to the above-mentioned process. Since a barrier layer is always deposited on both the vertical side walls and the bottom surface of an opening in the insulating layer, the presence of a barrier layer on the bottom of the opening causes several inconveniences. In order to ensure the conductivity of the metal lines, the barrier on the bottom of the opening must be made of an electrically conductive material. The adhesion between the barrier layer and the underlying conductive layer is not always good, thereby influencing the current flow between the different conductive levels. When the opening is afterwards filled with a metal in order to connect the metal layer underneath the insulating layer, the barrier layer between both metal layers has a detrimental effect on the electromigration behavior of the structure.
In addition, the exposure of the copper layers to the dielectric etch plasma in the classical scheme leads to the formation of residues on top of the copper. At the same time, copper sputtering, even though in very small amounts, and re-deposition onto the unprotected low-k side walls can not be avoided. Therefore, one has to make use of after-etch cleaning methods to remove the copper from the side walls of the opening etched in the insulating low-k material in order to prevent copper diffusion into the low-k material. After etching of the barrier, further cleaning methods are needed to clean up the residues on top of the copper in order to obtain a good via resistance. The different cleaning methods that are used must be compatible with the presence of the low-k material and must avoid sputtering of copper onto the side walls of the opening.
In the damascene metallization scheme, the first step is a pre-clean of the copper surface, which can be an in-situ pre-clean. This step includes the high risk of having re-deposition of copper on the low-k side wall, which may lead to its subsequent diffusion into the low-k material during the following barrier sputter process at higher temperature. In addition, it is clear that the pre-clean process step may also change the low k material properties leading to, e.g., an increased k value after the full process integration. The formation of TaN barrier layers with PVD techniques is difficult for high aspect ratio features, due to the intrinsic limited step coverage of such a process. Bad quality TaN barriers or layers which are too thin may lead to local breakdown of the copper barrier film and thus create a diffusion path for the copper.
The CMP process step makes use of two different slurries for, respectively, the CMP removal of copper and of the TaN. This makes the CMP process very difficult, very complex and very time-consuming and slurry-consuming, resulting in a high cost of ownership with medium process quality only.
When an opening is formed in a porous insulating material, the pores of the insulating material at the side wall of the opening are intersected, resulting in a rough side wall. Subsequently, the barrier layer is deposited by, e.g., PVD on the side walls of the opening, resulting in a barrier layer with the same profile as the rough side wall of the opening. This has a detrimental effect on the final device performance.
U.S. Pat. No. 5,818,071 discloses interconnect structures incorporating a silicon carbide layer as a diffusion barrier layer, more specifically a layer between a dielectric and a highly conductive

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