Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-22
2001-10-30
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S666000, C438S667000, C438S672000
Reexamination Certificate
active
06309960
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and to a method of fabricating a semiconductor device, and more particularly it relates to a semiconductor device and method of fabricating same which eliminates over-etching and achieves stable transistor characteristics.
2. Background of the Invention
In an interconnect technology making use of self-alignment process to form contacts in a semiconductor device, and particularly a method of forming a self-aligning contact using an etching stopper made of a silicon nitride film was accompanied by the following problems in the past.
FIG. 8
shows cross-section views of process diagrams illustrating the application of a general self-aligning contact process to a memory device.
As shown in FIG.
8
(
a
), a gate electrode
403
and an insulation film
404
made of a silicon nitride film are formed on a silicon substrate
401
and an element separation region
402
, and then a silicon nitride film
405
serving as an etching stopper is deposited so as to cover the gate electrode and the silicon substrate. Then after forming a BPSG film
406
as an interlayer insulation film, self-aligning contact etching is done to form a contact plug
410
. Then, after forming an interlayer insulation film
411
using a CVD process, a contact pattern is formed on photoresist
412
, this being used as a mask to etch the BPSG film
406
.
After the above, as shown in FIG.
8
(
b
), the silicon nitride film
405
is etched. When doing this, if the usual nitride film etching is done with a fluorocarbon gas such as CF
4
, because it is not possible to achieve a selection ratio with respect to the silicon substrate, the silicon substrate
401
is simultaneously etched.
As shown in
FIG. 9
, which is a simplified drawing of a transistor structure, each transistor on a p-type silicon substrate
414
, for example, is separated by a field oxide film
415
and, the transistor is formed by a gate electrode
416
, an n-type diffusion layer
418
that will serve as a source and drain, and a contact electrode
417
, when the n-type diffusion layer made of silicon is over-etched, there is current leakage in the direction A indicated in
FIG. 9
, the result being that it is not possible to achieve stable transistor characteristics.
While the above applies to the case in which an insulation film
404
over the gate electrode is a silicon nitride film, even in the case in which this insulation film
404
over the gate is a silicon oxide film, for the same reason as described above, the field oxide film
415
is etched, in which case there is current leakage in the direction B or the direction C indicated in
FIG. 9
, the result being that it is not possible to achieve stable transistor characteristics.
In the Japanese Unexamined Patent Publication (KOKAI) No. H9-205185, there is a method for removing the silicon nitride film from over the gate beforehand. This method, however, requires an extra lithography process, thereby causing the problem of an increased number of process steps.
Accordingly, in view of the above-noted drawbacks in the prior art, it is an object of the present invention to provide a novel method for fabricating a semiconductor device, whereby over-etching is prevented without the need to increase the number of lithography steps, and which achieves stable transistor characteristics.
SUMMARY OF THE INVENTION
In order to achieve the above-noted objects, the first aspect of the present invention has the following basic technical constitution.
Specifically, the first aspect of the present invention is a method for fabricating a semiconductor device having a contact plug, this method comprising the steps of: a first step of forming a polysilicon film and an insulation film on a semiconductor substrate, and then etching the polysilicon film and the insulation film to a prescribed shape, so as to form a gate electrode, after which an etching stopper is formed on an entire surface of the substrate and an interlayer insulation film is formed over the entire surface thereof; a second step of forming a contact hole that reaches the semiconductor substrate in the interlayer insulation film, so as to cause the etching stopper on the semiconductor substrate to be exposed; a third step of removing an exposed etching stopper on the semiconductor substrate; a fourth step of filling the contact hole to form a contact plug; a fifth step of removing a film that is deposited on the interlayer insulation film when the contact plug is formed, so as to expose the contact plug; a sixth step of etching the interlayer insulation film and removing the etching stopper on the gate electrode; a seventh step of forming an interlayer insulation film over an entire surface of the substrate; an eighth step of etching the interlayer insulation film so as to expose the etching stopper on a diffusion layer, and etching the insulation film of the gate electrode, so as to form contact holes on the diffusion layer and the gate electrode; a ninth step of removing the etching stopper exposed on the diffusion layer; and a tenth step of filling the contact hole formed by the eighth step and the ninth step, so as to form the contact plugs.
In a second aspect of the present invention, in the sixth step, CH
4
and CHF
3
gases are used as an etching gas.
In a third aspect of the present invention, in the sixth step, an etching rate of the interlayer insulation film and the etching stopper is higher than that of the contact plug formed in the fourth step.
In a fourth aspect of the present invention, in the eighth step, C
4
F
8
, Ar, CO, and O
2
gases are used as an etching gas.
In a fifth aspect of the present invention, in the eighth step, an etching rate of the interlayer insulation film is higher than that of the etching stopper.
In a sixth aspect of the present invention, in the ninth step, CHF
3
, Ar, and O
2
gases are used as an etching gas.
By doing the above, because there is no etching stopper on the gate electrode, over-etching of the diffusion layer and field oxide film are prevented when contact hole etching is done, thereby enabling the formation of a device having stable element separation characteristics.
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Bowers Charles
Hutchins, Wheeler & Dittmar
Kebede Brook
NEC Corporation
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