Method of fabricating a semiconductive device

Details Method of fabricating a semiconductive device Method of fabricating a semiconductive device

1999-05-21

2001-09-18

Mills, Gregory (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S305000, C438S592000, C438S595000, C438S655000, C438S682000, C438S696000, C438S734000, C438S714000, C438S740000

Reexamination Certificate

active

06291354

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the fabrication process of an integrated circuit (IC). More particularly this invention relates to the fabrication process of a semiconductor device.
2. Description of the Related Art
Metal silicide has been receiving an increased attention in the IC industry, for its exceptional physical properties such as high melting point, stability, and low resistivity. As the density of integrated circuits increases in the deep sub-micron integrated circuit technology, the line width, the contact area and the junction depth have been substantially decreased. According to the prior art, depositing a metal silicide of the polysilicon gate electrode or at the junction of the source/drain region effectively improves the performance of the device, reduces the electrical resistance and the delay in the signal transmission due to the electrical resistance and capacitance (RC). As the gate electrode resistance and the junction resistance are being reduced, the driving current, the response time, or the operational speed of the circuitry for the entire device is improved.
Currently the most commonly used technology in the fabrication of integrated circuits is known as the self-aligned silicide (salicide) process. As shown in
FIG. 1A
, in the self-aligned silicide process, the polysilicon gate electrode
102
is patterned and a spacer
108
is formed along the sidewall of the gate electrode on a wafer
100
. A metal layer
112
is then blanket-sputtered on the entire structure, followed by an annealing process. Silicide layers
114
and
116
are formed on the gate electrode
102
and on the junction such as the source/drain region. A wet etching process is used to remove the unreacted metal, to leave only the metal silicide
114
and
116
formed on the gate electrode
102
and the junction
110
as shown in FIG.
1
B. Since this process of forming silicide
114
and
116
eliminates the need to pattern with photolithography, this technique is therefore known as the self-aligned silicide process.
As mentioned above, a higher integration for integrated circuits is normally accompanied by a reduction of the device dimensions. To decrease the resistance of the polysilicon gate electrode, the tip of the spacer
108
mentioned previously is made to be lower than the surface of the polysilicon gate electrode
102
, so that a part of the sidewall of the polysilicon gate electrode
102
is exposed. The area of contact between the polysilicon gate electrode
102
and the metal layer
112
is therefore increased. Increasing the contact area between the polysilicon gate electrode and the metal layer proportionally increases the transformation of silicon on the polysilicon gate electrode
102
into metal silicide
114
. The purpose of lowering the gate
102
resistance is achieved according to the conventional method.
As indicated in
FIG. 2A
, a spacer
108
is formed conventionally by first depositing a liner layer
104
on the substrate
100
after the formation the gate electrode
102
on the substrate, followed by depositing a silicon oxide layer
106
on the substrate
100
. Subsequently, an anisotropic etching process is conducted to partially eliminate the silicon oxide layer
106
with the remaining silicon oxide layer surrounding the sidewall of the gate electrode
102
serving as a sidewall spacer
108
, as shown in FIG.
2
B. According to
FIG. 3
, in the process of creating the spacer, the tip of the spacer is overetched
302
and made to be lower than the gate electrode using an anisotropic dry etching process
300
, such that a portion of the sidewall of the polysilicon gate electrode is exposed.
Since the thickness of the liner layer
104
is not uniform, using the above anisotropic dry etching process
106
to overetch the silicon oxide layer will inevitably induce damages to the liner layer, and resulted in pitting on the substrate
100
as indicated in
118
of FIG.
2
B. Furthermore, while forming the spacer
108
using the dry etching process, the reactive ions rebound to a certain area on the substrate
100
after bombarding the spacer and form a microtrench
120
on the substrate
100
. The depth of the microtrench
120
increases with the increased duration of the etching process. Therefore, to form a spacer by using an anisotropic dry etching procedure
106
to overetch the silicon oxide layer easily damages the substrate
100
, and the reliability of the device is compromised.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a fabricating method for a semiconductor device that increases the exposed gate surface area.
The invention provides a fabricating method for a semiconductor device that further prevents damaging to the substrate resulted from the over-etching while forming the spacer thereby compromising the reliability of the device.
The invention provides a fabricating method for a semiconductor device comprises the following steps. A liner layer and an insulation layer are deposited on the substrate after a gate electrode is formed on the substrate. An anisotropic etching process is performed to remove a portion of the insulation layer, such that the remaining insulation layer on the gate and on the sidewall is at the same height as the spacer. An anisotropic etching process is performed to remove a portion of the spacer, such that the height of the spacer is lower than the gate electrode and the exposed gate surface area is increased.
The material used in this invention for the spacer mentioned above includes silicon oxide. The etching gas used in the isotropic etching process in removing a portion of the spacer includes sulfur hexafluoride and trifluoroamine. Since the fluorine free radicals generated by the etching gas selectively etches the silicon oxide and the liner layer, the liner layer is retained to protect the substrate surface during the isotropic dry etching process. The problems of pitting and microtrench formation, which may compromise the reliability of the device, are prevented.


REFERENCES:
patent: 4981810 (1991-01-01), Fazar et al.
patent: 5021353 (1991-06-01), Lowrey et al.
patent: 5672544 (1997-09-01), Pan
patent: 5731236 (1998-03-01), Chou et al.
patent: 5830798 (1998-11-01), Dennison et al.
patent: 6001690 (1999-12-01), Chien et al.
patent: 6140192 (2000-10-01), Hyang et al.

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