Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-04-02
2001-06-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S197000, C438S299000, C438S218000, C438S221000
Reexamination Certificate
active
06248643
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level.
2) Description of the Prior Art
Semiconductor applications require increasing packaging density. To accomplish the increased density, device geometries are scaled. Line widths are reduced and the number of levels is increased. As line widths decrease and the number of interconnecting levels increase, it becomes increasingly difficult to form conductor lines and contacts using conventional fabrication methods.
One problem which limits scaling is mask alignment. When more than one mask is used to fabricate a semiconductor, device sizes must be larger than theoretically required to compensate for misalignment between masks. With each additional mask, the alignment tolerances are increased.
Another problem which limits scaling is the errors induced by variations in exposure during phtolithography caused by uneven surface topography.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,316,975 (Maeda) shows a method for an interconnect process.
U.S. Pat. No. 5,316,957 (Spratt et al.) discloses a process for fabricating a bipolar transistor with a recessed contact.
U.S. Pat. No. 5,283,201 (Tsang et al.) teaches a contact process for a recessed gate formed in a trench on a substrate.
U.S. Pat. No. 5,087,584 (Wada et al.) shows a process for forming a floating gate memory array using a wordline trench.
U.S. Pat. No. 5,082,795 (Temple) shows a FET with a self aligned structure.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a new interconnection process suitable for reduced line width applications.
It is another object of the present invention to provide a new interconnection process using trench isolators, isolation spacers and selective contact plug formation to form self aligned contacts and reduce the number of photolithography steps.
It is another object of the present invention to provide a contact formation process which maintains planarization starting from the device level enhancing the photolithography resolution.
It is yet another object of the present invention to provide an economical and robust process for manufacturing interconnections for DRAM applications.
To accomplish the above objectives, the present invention provides a method for fabricating self-aligned contacts using elevated trench isolation, selective contact plug deposition and planarization starting at the device level. The process begins by successively forming a gate oxide layer and a first gate electrode layer on a silicon substrate. Next, fully planarized trench isolation regions are formed using sacrificial oxide and nitride layers and selective etching. A sacrificial pad oxide layer and a first sacrificial nitride layer are formed. The first sacrificial nitride layer, the sacrificial pad oxide layer, the first gate electrode layer, the gate oxide layer, and the silicon substrate are patterned to form trenches. A fill oxide layer is deposited in the trenches and over the first sacrificial nitride layer. An oxide etch is performed which recesses the fill oxide layer in the trenches below the level of the top of the first nitride layer. A second sacrificial nitride layer is formed on the fill oxide layer and over the first sacrificial nitride layer. Chemical-mechanical polishing is performed. Successive oxide etch, nitride etch and oxide etch steps are performed defining elevated trench isolation regions fully planarized with the first gate electrode layer. A silicide layer, an dielectric layer and a top nitride layer are formed. The top nitride layer, the dielectric layer, the silicide layer, the first gate electrode layer and the gate oxide layer are patterned forming gate structures between elevated trench isolation regions and conductive lines on elevated trench isolation regions. Spacers are formed on the sidewalls of the gate structures, the conductive lines and the elevated trench isolation regions. Then, self-aligned contact plugs are formed adjacent to the spacers.
The present invention provides considerable improvement over the prior art. One of the most significant limitations of scaling is the photolthography processing window. As the distance from the mask to the wafer increases, resolution decreases. Non-planar topography limits resolution because of how close the mask can be to the wafer. Because the wafer is fully planarized prior to the photolithography step, the present invention can acheive superior resolution.
Layer surfaces that are not parallel to the top surface can cause defraction during photolithography resulting in distortion of the mask image. The improved planarization of the present invention starting from the device level prevents such distortion. Because structures do not have to be sized to compensate for this distortion the present invention facilitates the use of smaller strucures.
Multiple masking and etching steps increase complexity, processing time and misalignment error accumulation. The present invention provides simplified photolithography and etching processes for contact hole formation due to the self-aligned contact formation process.
Polysilicon contact plugs limit device speed due to the contact resistance. The present invention provides reduced contact resistance due to a silicon or tungsten contact.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5082795 (1992-01-01), Temple
patent: 5087584 (1992-02-01), Wada et al.
patent: 5231051 (1993-07-01), Baldi et al.
patent: 5283201 (1994-02-01), Tsang et al.
patent: 5316957 (1994-05-01), Spratt et al.
patent: 5316975 (1994-05-01), Maeda
patent: 5677227 (1997-10-01), Yang et al.
patent: 5706164 (1998-01-01), Jeng
patent: 5721154 (1998-02-01), Jeng
patent: 5753555 (1998-05-01), Hada
patent: 5789792 (1998-08-01), Tsutsumi
Hsieh Chien-Sheng
Jeng Erik S.
Lin Wei-Ray
Sheu Bor-Ru
Yang Fu-Liang
Ackerman Stephen B.
Bowers Charles
Saile George O.
Smoot Stephen W.
Stoffel William J.
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