Method of fabricating a read only memory in MOS technology, and

Details Method of fabricating a read only memory in MOS technology, and Method of fabricating a read only memory in MOS technology, and

1996-01-30

1997-10-21

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 52, 437 45, H01L 218246

Patent

active

056795947

ABSTRACT:
A method of fabricating a read only memory consisting of a matrix of arrays of enhancement-mode or depletion-mode programmed MOS transistors that consists, on a silicon substrate (SU) of a first conduction type, in defining by masking, retrograde wells of the same conduction type as that of the substrate, and then retrograde wells of conduction type opposite to that of the substrate. Removal of the protective oxide allows thus to predefine the enhancement-mode and depletion-mode transistors.

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Patent Abstracts of Japan, vol. 012 No. 089 (E-592), Mar. 23, 1988 and JP-A-62 224069 (Hitachi Ltd.), Oct. 2, 1987 *abrege*.

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