Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
2002-12-13
2003-09-30
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S149000, C438S151000, C438S197000, C438S221000, C438S222000, C438S225000, C438S226000, C438S311000, C438S353000, C438S355000, C438S357000, C438S359000, C438S362000, C438S424000, C438S412000, C438S413000, C438S442000, C438S406000, C438S733000, C438S735000, C438S745000
Reexamination Certificate
active
06627515
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form portions of a device on an insulator layer without forming a floating body device.
(2) Description of Prior Art
Devices formed in silicon layers which in turn completely overlying insulator, have allowed reductions in performance degrading parasitic capacitances to be realized. The increased performance of devices fabricated using silicon on insulator (SOI), technology however is achieved at higher processing costs when compared to counterpart devices formed in, and only overlying, semiconductor material. The increased cost of SOI devices is attributed to the additional processing used to form the SOI layer, with a first option featuring bonding procedures, where one of the bonded wafers features the insulator layer, followed by thinning of the bonded semiconductor wafer. A second option, also resulting in increased processing cost, is formation of the SOI layer via implantation of oxygen ions into a semiconductor wafer followed by an anneal cycle resulting in an silicon oxide layer located underlying a thin portion of unimplanted silicon. In addition to the increased processing costs incurred with the SOI technology, the presence of an insulator layer on the entire surface of the semiconductor can result in a floating body effect, wherein the semiconductor substrate is floating with respect to the device channel region. This can result in unwanted threshold voltages thus adversely influencing designed operating conditions.
This invention will describe a method of fabricating a device where only portions of the device overlay insulator layer, wherein the overlaid insulator layer is buried oxide regions, not an entire insulator layer as is the case with SOI layers. The use of buried oxide regions still allow decreased parasitic capacitance and increased performance to be realized, without experiencing the negative device parameters encountered with SOI, floating body type devices. Prior art such as Chu et al, in U.S. Pat. No. 6,251,751 B1, Juengling, in U.S. Pat. No. 5,670,412, Huang, in U.S. Pat. No. 6,235,567 B1, and Chu et al, in U.S. Pat. No. 5,963,817, describe methods of forming buried oxide regions, however none of these prior art describe the unique combination of process steps of this present invention, allowing optimum buried oxide regions to be formed and overlaid by specific portions of a semiconductor device.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a semiconductor device in a silicon layer, wherein specific portions of the device overlying an insulator shape.
It is another object of this invention to fabricate the semiconductor device in a silicon layer where a portion of the device overlays a silicon alloy layer, and where other portions of the device overlay an insulator shape, wherein the insulator shape is formed from oxidation of portions of the silicon alloy layer.
It is still another object of this invention to fabricate the semiconductor device in a silicon layer where a portion of the device overlays a silicon alloy layer, and where other portions of the device overlay an insulator shape, wherein the insulator shape is formed via insulator filling of an isotropically defined opening in the silicon alloy layer.
In accordance with the present invention a method of forming a semiconductor device in a silicon layer, wherein portions of the semiconductor device overlay a silicon alloy layer while other portions of the semiconductor device overlay an insulator shape formed in the silicon alloy layer, is described. After deposition of a silicon alloy layer on a,semiconductor substrate surface, a strained silicon layer is epitaxially grown. An oxidation resistant insulator layer is deposited followed by a patterning procedure resulting in a composite shape comprised of an oxidation resistant insulator shape on a strained silicon shape, exposing regions of the silicon alloy layer located between the composite shape. A first embodiment of this invention features formation of oxidation resistant spacers on the sides of the composite shapes, followed by an oxidation procedure used to form a silicon alloy oxide shape in regions of the silicon alloy located between the composite shapes, as well forming the silicon alloy oxide shape in portions of the silicon alloy layer underlying edges of the strained silicon shape. Removal of all oxidation resistant material results in a strained silicon shape, with a center portion of this shape overlying the silicon alloy layer, while edges of the strained silicon shape are located overlying the silicon alloy oxide shape. Subsequent device fabrication features the formation of specific device elements in regions of the strained silicon layer shape overlying the silicon alloy oxide shape.
A second embodiment of this invention again features the a composite shape on a silicon alloy layer, with the composite shape comprised of a silicon oxide shape on a strained silicon shape. After formation of silicon oxide spacers on the sides of the composite shapes, an isotopic dry etch procedure is used to remove portions of the silicon alloy layer located between composite shapes, as well as removing portions of the silicon alloy layer located under the edges of the silicon shape. Refilling of the isotropic openings in the silicon layer via deposition of a silicon oxide layer is followed by a planarization procedure, resulting in a strained silicon shape embedded by silicon oxide, with the center portion of the strained silicon layer overlying the silicon alloy layer while the edges of the strained silicon shape are located overlying the refilled silicon oxide layer. Subsequent device fabrication will feature the formation of specific device elements in regions of the strained silicon shape located overlying the silicon alloy oxide shape.
REFERENCES:
patent: 6251751 (2001-06-01), Chu et al.
patent: 6255147 (2001-07-01), Buynoski
patent: 2002/0008289 (2002-01-01), Murota et al.
patent: 2002/0125502 (2002-09-01), Baba et al.
Guo Jyh-Chyurn
Hu Chenming
Lin Da-Chi
Tseng Horng-Huei
Isaac Stanetta
Niebling John F.
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