Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-04-21
2010-10-26
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
07820538
ABSTRACT:
A polycrystalline silicon layer is deposited on a gate dielectric and then a portion thereof is re-oxidized so as to form a thin layer of oxide between the poly-Si layer and the underlying gate dielectric. Subsequently, the poly-Si layer is converted to a fully-silicided form so as to produce a FUSI gate. The gate dielectric can be a high-k material, for example a Hf-containing material, or SION, or another non-SiO2dielectric. The barrier oxide layer is preferably less than 1 nm thick.
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80 nm poly-Si gate CMOS with HfO2 gate dielectric Hobbs, C.; Tseng, H.; Reid, K.; Taylor, B.; Dip, L.; Hebert, L.; Garcia, R.; Hegde, R.; Grant, J.; Gilmer, D.; Franke, A.; Dhandapani, V.; Azrak, M.; Prabhu, L.; Rai, R.; Bagchi, S.; Conner, J.; Backer, S.; Dumbuya, F.; Nguyen, B.; Tobin, P.; Electron Devices Meeting, 2001. IEDM Technical Digest. International Dec. 2-5, 2001 pp. 30.1.1-30.1.4.
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Freescale Semiconductor Inc.
Garber Charles D
Stevenson André C
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