Method of fabricating a monolithic integrated circuit with at le

Details Method of fabricating a monolithic integrated circuit with at le Method of fabricating a monolithic integrated circuit with at le

1994-03-04

1995-05-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437162, 437 59, H01L 21265

Patent

active

054119006

ABSTRACT:
The invention relates to a method of making a monolithic integrated circuit with at least one CMOS field-effect transistor and one npn bipolar transistor wherein a thin oxide layer is covered with a protective polysilicon layer in both the bipolar-transistor area and the field-effect-transistor area.

REFERENCES:
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patent: 5001081 (1991-03-01), Tuntasood et al.
patent: 5128272 (1992-07-01), Ramde
patent: 5187109 (1993-02-01), Cook et al.
patent: 5196356 (1993-03-01), Won et al.
Wolf, "Silicon Processing for the VLSI Era--vol II", pp. 491-495, 1990.
New CMOS Technologies, Solid State Devices, 1980, pp. 114-117.
A single-Poly C-BiCMOS Process with Advanced ITLDD CMOS and Self-Aligned Vertical NPN, PNP Devices Technical Developments, Motorala, Inc., Jul. 1991, pp. 135-136.

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