Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2001-10-12
2003-09-16
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06620701
ABSTRACT:
TECHNICAL FIELD
Embodiments of the present invention relate generally to the fabrication of semiconductor devices, and more particularly to metal-insulator-metal capacitors (MIMCap's).
BACKGROUND
Semiconductor devices are widely used for integrated circuits for electronic applications, including radios, televisions and personal computing devices, as examples. Such integrated circuits typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
The manufacturing process flow for semiconductors is generally referred to in two time periods: front-end-of-line (FEOL) and back-end-of-line (BEOL). Higher temperature processes are performed in the FEOL, during which impurity implantation, diffusion and formation of active components such as transistors are performed on a semiconductor substrate of a wafer. Lower temperature processes take place in the BEOL, which is generally considered to begin upon the formation of the first metallization layer on the wafer.
Capacitors are elements used extensively in semiconductor devices for storing an electric charge. Capacitors essentially comprise two conductive plates separated by an insulator. The capacitance, or amount of charge held by the capacitor per applied voltage, is measured in farads and depends upon the area of the plates, the distance between them, and the dielectric value of the insulator, as examples. Capacitors are used in filters, in analog-to-digital converters, memory devices, and control applications, and many other types of semiconductor devices.
One type of capacitor is a MIMCap, which is used frequently in mixed signal devices and logic devices, for example. MIMCap's are used to store a charge in a variety of semiconductor devices, such as mixed signal and analog products. MIMCap's typically require a much lower capacitance than deep trench memory capacitors used in dynamic random access memory (DRAM) devices, for example. A MIMCap may have a capacitance requirement of 1 fF/micrometer
2
, for example.
Recently, there has been an increase in demand for MIMCap's embedded in BEOL integrated circuits. MIMCap's typically are horizontal MIMCap's comprising two metal plates that sandwich a dielectric parallel to the wafer. Prior art horizontal MIMCap's are manufactured in the BEOL by forming the bottom capacitive plate in the first or subsequent horizontal metallization layer of a semiconductor wafer. A capacitor dielectric is deposited over the bottom capacitive plate, and a second mask, pattern and etch step is required to form the top capacitive plate. Alternatively, MIMCap's are formed between horizontal metallization layers in the BEOL in additional horizontal layers, with each plate requiring a separate pattern and etch level.
A horizontal MIMCap requires a large amount of surface area on a semiconductor wafer. A horizontal MIMCap is a large flat capacitor positioned parallel to the wafer surface covering a large area of the chip, and does not provide a high area efficiency. As the demand for the capacitance increases, it is desirable to develop MIMCap's that utilize the chip area as efficiently as possible.
A vertical MIMCap, described in U.S. patent application Ser. No. 09/742,918 for “Self-Aligned Double-sided Vertical MIMCap”, is incorporated herein by reference, discloses a vertical MIMCap structure and method that improves the efficiency of the use of chip surface area.
What is needed in the art is a method of fabricating a MIMCap that utilizes wafer area more efficiently and minimizes process complexity than prior art MIMCap's processes.
SUMMARY OF THE INVENTION
Embodiments of the present invention include methods of fabricating high area efficiency MIMCap's embedded in damascene BEOL processes with minimum process complexity added to the commonly-practiced BEOL processes. The method includes fabricating a MIMCap having plates with both vertical and horizontal capacitive regions in a process requiring only one mask and lithography step.
Disclosed is a method of fabricating a MIMCap, comprising providing a wafer having a workpiece, depositing a first insulating layer over the wafer workpiece, and forming a plurality of first conductive lines within the first insulating layer, where the first conductive lines comprising a first conductive material. The method includes depositing a second insulating layer, depositing a resist over the second insulating layer, patterning the resist with a predetermined pattern, and removing portions of the resist to expose portions of the second insulating layer. At least the exposed second insulating layer and portions of the first insulating layer are removed, leaving portions of the first conductive lines exposed. The remaining resist is removed, and a capacitor dielectric is deposited over the first conductive lines. A second conductive material is deposited over the capacitor dielectric to form second conductive lines.
Also disclosed is a method of fabricating a vertical/horizontal MIMCap, comprising providing a wafer having a workpiece, depositing a first insulating layer over the wafer workpiece, forming a plurality of trenches within the first insulating layer, and filling the trenches with a first conductive material to form first conductive lines within the first insulating layer. A cap layer is deposited over the first conductive lines and first insulating layer, a second insulating layer is deposited over the cap layer, and a resist is deposited over the second insulating layer. The method includes patterning the resist with a predetermined pattern defining a MIMCap, removing portions of the resist to expose portions of the second insulating layer, removing the exposed second insulating layer, the cap layer, and portions of the first insulating layer, leaving portions of the first conductive lines exposed, and removing the remaining resist. A capacitor dielectric is deposited over the first conductive lines, and a second conductive material is deposited over the capacitor dielectric to form second conductive lines. Portions of the first conductive lines are coupled together, and portions of the second conductive lines are coupled together, wherein the first and second conductive line portions comprise the plates of a MIMCap, the MIMCap plates having horizontal and vertical portions.
Advantages of the invention include providing a method of fabricating a vertical/horizontal MIMCap that utilizes wafer area more efficiently than prior art horizontal MIMCap's. The vertical/horizontal MIMCap described herein may be five times smaller, for example, than horizontal MIMCap's producing the same capacitance. Only one additional mask level is required to implement embodiments of the method. Forming the first conductive lines in the first insulating layer using a damascene process results in a more accurate transfer of the pattern for the conductive lines. The formation of the second conductive lines is self-aligned, being formed between the first conductive lines, and thus, do not require a separate etch process step.
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Armacost, et al., “A High Reliability Metal Insulator Metal Capacitor for 0
Chaudhuri Olik
Kebede Brook
Slater & Matsil L.L.P.
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