Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-10-31
2006-10-31
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257SE29266
Reexamination Certificate
active
07129547
ABSTRACT:
A method of fabricating a MOSFET device featuring a raised source/drain structure on a heavily doped source/drain region as well as on a portion of a lightly doped source/drain (LDD), region, after removal of an insulator spacer component, has been developed. After formation of an LDD region a composite insulator spacer, comprised of an underlying silicon oxide spacer component and an overlying silicon nitride spacer component, is formed on the sides of a gate structure. Formation of a heavily doped source/drain is followed by removal of the silicon nitride spacer resulting in recessing of, and damage formation to, the heavily doped source/drain region, as well as recessing of the gate structure. Removal of a horizontal component of the silicon oxide spacer component results in additional recessing of the heavily doped source/drain region, and of the gate structure. A selective epitaxial growth procedure is then used to form a raised, single crystalline silicon structure on the recessed and damaged heavily doped source/drain and LDD regions, while a polycrystalline silicon structure is grown on the underlying recessed gate structure. Metal silicide is then formed on the raised, single crystalline silicon structure and on the polycrystalline silicon structure.
REFERENCES:
patent: 5296727 (1994-03-01), Kawai et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5949105 (1999-09-01), Moslehi
patent: 5994747 (1999-11-01), Wu
patent: 6197645 (2001-03-01), Michael et al.
patent: 6287926 (2001-09-01), Hu et al.
patent: 6445042 (2002-09-01), Yu et al.
“Raised Source/Drains with Disposable Spacers for Sub 100 nm CMOS Technologies” Meyer et al., 2001, pp. 5-3-1 to 5-3-4.
Chang Chih-Sheng
Wang Yin-Pin
Liu Benjamin Tzu-Hung
Taiwan Semiconductor Manufacturing Co. Ltd.
Thomas Kayden Horstemeyer & Risley
Tran Minhloan
LandOfFree
Method of fabricating a high performance MOSFET device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a high performance MOSFET device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a high performance MOSFET device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3672360