Method of fabricating a heterojunction bipolar transistor

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction

Reexamination Certificate

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C438S338000

Reexamination Certificate

active

06855613

ABSTRACT:
A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.

REFERENCES:
patent: 4214966 (1980-07-01), Mahoney
patent: 4301188 (1981-11-01), Niehaus
patent: 4889831 (1989-12-01), Ishii et al.
patent: 5340755 (1994-08-01), Zwicknagl et al.
patent: 5420052 (1995-05-01), Morris et al.
patent: 5620909 (1997-04-01), Lin et al.
patent: 5625206 (1997-04-01), Chandrasekhar et al.
patent: 5656515 (1997-08-01), Chandrasekhar et al.
patent: 5698460 (1997-12-01), Yang et al.
patent: 5801093 (1998-09-01), Lin
patent: 5903037 (1999-05-01), Cho et al.
patent: 5907165 (1999-05-01), Hamm et al.
patent: 6137125 (2000-10-01), Costas et al.
patent: 6165859 (2000-12-01), Hamm et al.
patent: 6294018 (2001-09-01), Hamm et al.
patent: 6310368 (2001-10-01), Yagura
patent: 08-017798 (1996-01-01), None
patent: 10-050720 (1998-02-01), None
Kouhei Morizuka et al., “AlGaAs/GaAs HBT's Fabricated by a Self-Alignment Technology Using Polyimide for Electrode Separation” IEEE, Electron Device Letters, vol. 9, No. 11 Nov. 1998, pp 598-600.*
“Evaluation of Encapsulation and Passivation of InGaAs/InP DHBT Devices for Long-Term Reliability”, by Kopf, R. F. et al.,Journal of Electronic Materials, vol. 27, No. 8, pp. 954-960 (1998).
“ECR Plasma Etch Fabrication of C-Doped Base InGaAs/InP DHBT Structures: A Comparison of CH4/H2/Ar vs BCI3/N4Plasma Etch Chemistries”, by Kopf, R. F. et al.,Journal of Electronic Materials, vol. 27, pp. 69-72 (1998).
“Gallium Arsenide Processing Techniques”, by Williams, R. E., published by The Artech Microwave Library, pp. 126-129.

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