Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-07-20
2003-02-18
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
Reexamination Certificate
active
06521517
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a MOS (Metal Oxide Semiconductor) transistor, and a method of manufacturing the same. As used herein, the term “MOS transistor” denotes a field effect transistor having a MOS structure, and is also used as the concept including the case where not only an oxide but also another insulator is employed as a gate insulating film.
2. Description of the Background Art
FIG. 30
is a cross section illustrating the step of forming a gate electrode in a conventional method of manufacturing a MOS transistor. In the surface of a semiconductor substrate
1
, an active region is defined by an element isolation region
9
, such as a trench isolation. A gate insulating film
2
is then formed on the surface of the semiconductor substrate
1
by performing thermal oxidation.
Subsequently, a stacked structure comprising a polysilicon layer
3
, silicide layer
4
, and a nitride film
5
that functions later as a hard mask, is temporarily formed on the entire surface, and an anti-reflection coating film (not shown) is stacked thereon. After a resist (not shown) is applied to the entire surface, a pattern transfer and its development are performed so that the resist is of a predetermined shape. By using the resulting resist pattern as a mask, the nitride film
5
is formed in a predetermined shape by etching. By using the resulting nitride film
5
as a hard mask, an etching is conducted so that the silicide layer
4
and polysilicon layer
3
are made into the same shape as the nitride film
5
, when viewed from above, thereby obtaining the structure shown in FIG.
30
.
When an oxide film is employed as a gate insulating film
2
, the etching of the polysilicon layer
3
can be performed in a high etching selective ratio to the gate insulating film
2
. Therefore, even when the polysilicon layer
3
is further etched from the state that it remains only beneath the nitride film
5
, it is able to reduce the amount of etching of the gate insulating film
2
.
Thus, the feature that the area making a direct contact with a gate insulating film is formed with polysilicon, enables to reduce the difference in the work function with silicon, as compared to the case where an NMOS transistor and PMOS transistor are both formed with a single metal or silicide.
Recently, as semiconductor devices have lower operating current and higher speed, its gate insulating film becomes thinner. Further, it is intended that a gate nitride film having a higher dielectric constant is substituted for a gate oxide film.
However, the etching selective ratio of a nitride film to polysilicon cannot be made so high as that of an oxide film to polysilicon. Therefore, the adoption of a nitride film as a gate insulating film
2
and the adoption of polysilicon as the portion of a gate electrode making a direct contact with the gate insulating film
2
have caused a drawback requiring a rigid control during etching for modifying the polysilicon as the gate electrode.
FIGS. 31 and 32
are cross sections illustrating an aspect that can occur in the event of failure of the rigid control of the above etching. That is,
FIG. 31
shows the state that a gate insulating film
2
used instead of the gate oxide film
21
in
FIG. 30
is broken during the etching of polysilicon, and an etchant reaches the semiconductor substrate
1
, thereby forming a void
11
in the semiconductor substrate
1
. Even if an oxide film is employed as the gate insulating film
2
, such a problem becomes significant when the thickness of the oxide film is reduced.
Even if the etchant does not reach the semiconductor substrate
1
, when the gate insulating film
2
becomes thin, an etching induced damage remains in the semiconductor substrate
1
.
FIG. 32
shows the state that an etching induced damage
12
occurs in the semiconductor substrate
1
. The etching induced damage
12
acts as the trap of carrier. For instance, in an LDD (Lightly Doped Drain) structure, an extension region is formed which is continuous with a source/drain, and has a lower impurity concentration than that of the source/drain. This trap reduces the carrier concentration, in particular, the carrier concentration in the extension region, and also increases the parasitic resistance of a transistor. An increase in parasitic resistance causes an increase in heat generation and a reduction in operating speed, on an integrated circuit.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type; (b) forming a first conductive layer on the gate insulating film; (c) selectively forming a second conductive layer on the first conductive layer; (d) selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer; and (e) forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left in the step (d).
According to a second aspect, the method of the first aspect is characterized in that the first conductive layer is composed of a doped semiconductor, and the doped semiconductor is selectively oxidized in the step (d), the method further comprising the step, after the step (e), of: (f) performing an etching of the insulating layer and the gate insulating film so that these are selectively removed to expose the source/drain regions.
Preferably, the method of the second aspect further comprises the step of: (g) performing a silicidation of the source/drain regions exposed in the step (f).
According to a third aspect, the method of the second aspect further comprises the step, after the step (c) and before the step (d), of: (g) implanting impurities to the surface of the semiconductor substrate by using the second conductive layer as a mask, so as to form a pair of extension regions of the second conductivity type in the surface of the semiconductor substrate.
According to a fourth aspect, the method of the second aspect is characterized in that the second conductivity layer is composed of metal, and, in the step (d) an oxidation is conducted in an oxidizing atmosphere having a reducing component.
Preferably, the reducing component includes hydrogen.
According to a fifth aspect, the method of the first aspect further comprises the step, after the step (c) and before the step (d), of: (f) forming a coating layer covering the second conductive layer and the first conductive layer, and is characterized in that in the step (d), insulating property is imparted to said coating layer and said coating layer becomes part of the insulating layer.
According to a sixth aspect, the method of the fifth aspect is characterized in that the first conductive layer is composed of a first semiconductor doped, that the coating layer is composed of a material that is an oxidizable material, and that the first semiconductor and the material are oxidized in the step (d), the method further comprising the step, after the step (e), of: (f) selectively removing the insulating film and the gate insulating film to expose the source/drain region.
According to a seventh aspect, the method of the sixth aspect further comprises the step, after the step (d) and before the step (f), of: (g) implanting impurities to the surface of the semiconductor substrate by using, as a mask, the second conductive layer and the coating layer present on the side of the second conductive layer, thereby to form a pair of extension regions of the second conductivity type in the surface of the semiconductor substrate.
According to an eighth aspect, the method of the sixth aspect is characterized in that the second conductive layer is composed of metal, and that the coating layer is composed of a second
Kitazawa Masashi
Ota Kazunobu
Shirahata Masayoshi
Lebentritt Michael S.
Mitsubishi Denki & Kabushiki Kaisha
Owens Beth E.
LandOfFree
Method of fabricating a gate electrode using a second... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a gate electrode using a second..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a gate electrode using a second... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3129318