Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1996-12-17
2000-07-18
Nelms, David
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438672, 438675, H01L 21311
Patent
active
060907169
ABSTRACT:
In the present method, a semiconductor substrate is provided with an epitaxial layer thereon. A source/drain region is provided in a portion of the epitaxial layer, and a plurality of trenches are etched in the epitaxial layer and extend into the substrate, to define a plurality of mesas.
An oxide layer of generally uniform thickness is provided over the mesas and in the trenches, and a polysilicon layer is provided over the oxide layer and is etched so that the oxide layer overlying the mesas is exposed, and the top surface of the polysilicon within the trenches is below the level of the tops of the mesas.
A layer of spin-on-glass (SOG) is provided, and the SOG layer and oxide layer are etched substantially to the level of the tops of the mesas, to expose the tops of the mesas and to leave the portions of the SOG over the respective polysilicon portions in the trenches substantially coplaner with the tops of the mesas.
A conductive layer is provided over the remaining portions of the SOG layer and the tops of the mesas.
REFERENCES:
patent: 4704368 (1987-11-01), Goth et al.
patent: 5122848 (1992-06-01), Lee et al.
patent: 5316959 (1994-05-01), Kwan et al.
patent: 5358884 (1994-10-01), Violette
patent: 5473176 (1995-12-01), Kakumoto
patent: 5742472 (1998-04-01), Lee et al.
patent: 5793082 (1998-08-01), Bryant
patent: 5869861 (1999-02-01), Chen
Syau, et al., "Extended Trench-Gate Power UMOSFET Structure with Ultralow Specific On-Resistance", Electronics Letters, Apr. 23, 1992, vol. 28, No. 9, pp. 865-867.
Syau, et al., "Comparison of Ultralow Specific On-Resistance UMOSFET Structures: The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's", IEEE Transactions on Electron Devices, vol. 41, No. 5, May 1994, pp. 800-808.
Chang Mike F.
Cheung Brian
Floyd Brian H.
Ho Chin H.
Juang Min
Berry Renee R.
Nelms David
Siliconix incorporated
Steuber David E.
LandOfFree
Method of fabricating a field effect transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a field effect transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a field effect transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2036569