Method of fabricating a feature in an integrated circuit using a

Details Method of fabricating a feature in an integrated circuit using a Method of fabricating a feature in an integrated circuit using a

1998-09-24

2000-12-19

Bowers, Charles

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

438314, 438318, 438309, H01L 21331

Patent

active

061626961

ABSTRACT:
A method of fabricating a feature on a substrate is described. In one embodiment, the fabricated feature is the gate electrode of an MOS transistor. A feature layer is formed on the substrate with a patterned edge definition layer then formed on the feature layer. Next, a spacer layer is formed adjacent to an edge of the patterned edge definition layer. Finally, the feature layer is etched, forming the transistor gate electrode from the feature layer that remains under the spacer.

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J.T. Hortsmann, et al.; "Characterization of Sub-100 nm-MOS-Transistors Processed by Optical Lithography and a Sidewall-Etchback Technique"; Faculty of Electrical Engineering. University of Dortmund, Emil-Figge-Str. 68, D 44220 Dortmund, Germany; 4 pages total.
H. Liu et al.; "100 nm CMOS Gates Patterned with 3 below 10nm" SPIE-The International Society for Optical Engineering. vol. 3331. pp. 375-381.

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