Method of fabricating a dual damascene structure

Details Method of fabricating a dual damascene structure Method of fabricating a dual damascene structure

1998-12-04

2000-11-28

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438754, 438687, 438691, 438723, 438724, H01L 21302

Patent

active

061535281

ABSTRACT:
A method for fabricating a dual damascene structure is provided. The method contains providing a substrate, which has a patterned metal layer on it. A first liner oxide layer, a first seed layer are sequentially formed over the substrate. The first seed layer is patterned to form a first opening above the patterned metal layer to expose the first liner oxide layer. A first dielectric layer is formed over the substrate. The first dielectric layer includes a first porous dielectric layer on the first seed layer, and a first normal dielectric layer on the exposed portion of the first liner oxide layer. A first cap layer is formed over the first dielectric layer, and is planarized. An etching stop layer with a second opening above the first opening to expose the first cap layer is formed on the first cap layer. With the same formation mechanism, a second liner oxide layer, a second seed layer with a third opening above the second opening, a second porous dielectric layer, a second cap layer are formed over the substrate. A mask layer is formed over the second cap layer. Patterning the above layers forms a damascene opening in the first normal dielectric layer and the second normal dielectric layer. Filling the dual damascene opening with metallic material forms a dual damascene structure.

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patent: 5849367 (1998-12-01), Dixit et al.
patent: 5891804 (1999-04-01), Havemann et al.
patent: 5950102 (1999-09-01), Lee
patent: 5985762 (1999-11-01), Geffken et al.
patent: 5989623 (1999-11-01), Chen
patent: 6008540 (1999-12-01), Lu et al.

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