Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-04-30
2002-08-20
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S702000, C438S703000
Reexamination Certificate
active
06436836
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention pertains to a fabrication method for a DRAM cell configuration, that is to say a dynamic random access memory cell configuration, whose memory cells each comprise a transistor and a capacitor.
In such a DRAM cell configuration, the information of a memory cell is stored in the form of a charge on the capacitor. The transistor and the capacitor of the memory cell are connected to one another in such a way that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
Endeavors are generally made to produce DRAM cell configurations with a high packing density, that is to say a small space requirement per memory cell.
European published patent specification EP 0 852 396 (see commonly assigned U.S. Pat. Nos. 5,937,296 and 6,150,210) describes a DRAM cell configuration in which, in order to increase the packing density, a transistor of a memory cell is arranged above a storage capacitor of the memory cell. Active regions of the memory cells are in each case surrounded by an insulating structure arranged in a substrate. A depression is produced in the substrate for each memory cell, a storage node of the storage capacitor being arranged in the lower region of the depression and a gate electrode of the transistor being arranged in the upper region of the depression. An upper source/drain region, a channel region and a lower source/drain region of the transistor are arranged one above the other in the substrate. The lower source/drain region is connected to the storage node at a first sidewall of the depression. The insulating structure adjoins a second sidewall—opposite the first sidewall—of the depression, with the result that the storage node does not adjoin the substrate there. A bit line adjoins the upper source/drain region and runs above the substrate. In order to fabricate the DRAM cell configuration, firstly the insulating structure is produced. The bit line is produced on a surface of the substrate. The upper source/drain region is produced by the diffusion of dopant from the bit line into the substrate. The depression is produced in a manner adjoining the insulating structure. Sidewalls of the depression are provided with a capacitor dielectric. The depression is filled with doped polysilicon up to a first height, which lies in the region of the insulating structure. Uncovered parts of the capacitor dielectric are removed. Afterward, the depression is filled with doped polysilicon up to a second height, which is higher than the first height and lies in the region of the insulating structure, with the result that the polysilicon forms a storage node which adjoins the substrate at the first sidewall of the depression between the first height and the second height. The lower source/drain region is formed by the diffusion of dopant from the storage node into the substrate.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method of producing a DRAM cell configuration which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and which process leads to a DRAM cell having a higher packing density in comparison with the prior art.
With the above and other objects in view there is provided, in accordance with the invention, a method of fabricating a DRAM cell configuration, which comprises the following steps: producing a depression for a capacitor of a memory cell of the DRAM in a substrate;
producing in the depression an insulation and a storage node of the capacitor, wherein the capacitor is at least partly isolated from the substrate by the insulation;
producing a spacer of silicon above the storage node in the depression along sidewalls of the depression, by deposition, etching back, and inclined implantation of silicon, wherein a first part of the spacer and a second part, opposite the first part, of the spacer are doped differently;
patterning the spacer by removing one of the first part of the spacer and the second part of the spacer utilizing the different doping thereof;
altering the insulation and a first part of the storage node disposed under the removed part of the spacer, such that either the first part of the storage node or a second part of the storage node disposed under the remaining part of the spacer, adjoins the substrate, and thereby utilizing the patterned spacer as a mask;
producing a transistor of the memory cell such that a first source/drain region is formed in the substrate adjoining the storage node;
producing and connecting a word line to a gate electrode of the transistor; and
producing a bit line running transversely with respect to the word line and connecting the bit line to the memory cell.
In other words, the above objects are satisfied with the method of fabricating a DRAM cell configuration, in which a depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor, which is at least partly isolated from the substrate by the insulation, are produced in the depression. By deposition, etching back and inclined implantation of silicon, a spacer made of silicon is produced above the storage node in the depression along sidewalls of the depression, in which a first part of the spacer and a second part—opposite to the first part—of the spacer are doped differently. The spacer is patterned by either the first part of the spacer or the second part of the spacer being removed by utilizing their different doping. A first part of the storage node, said first part being arranged under the removed part of the spacer, and the insulation are altered in such a way that either the first part of the storage node or a second part of the storage node, said second part being arranged under the remaining part of the spacer, adjoins the substrate, the patterned spacer serving as a mask. A transistor of the memory cell is produced in such a way that a first source/drain region is formed in the substrate in a manner adjoining the storage node. A word line is produced and connected to a gate electrode of the transistor. A bit line running transversely with respect to the word line is produced and connected to the memory cell.
The spacer is composed, for example, of polysilicon or amorphous silicon.
The patterned spacer acts as a mask in that the remaining part of the spacer protects the second part of the storage node from process steps.
Since the storage node does not adjoin the substrate both with its first part and with its second part, an adjacent memory cell can be arranged in direct proximity to the depression, without leakage currents occurring between the storage node and the adjacent memory cell. The storage node is isolated from the adjacent memory cell by the insulation in the depression. An insulation structure outside the depression which isolates the storage node from the adjacent memory cell is not necessary, with the result that the DRAM cell configuration can have a particularly high packing density. The single-sided alteration of the storage node and of the insulation is effected in a self-aligned manner, that is to say without the use of a mask to be aligned. This is a major advantage with regard to a high packing density since there is no need to take account of a space requirement for alignment tolerances.
Since insulation structures which are arranged outside the depression and reach down into regions of the first source/drain regions of the transistors of the memory cells are not required, the invention makes it possible to fabricate a DRAM cell configuration in which channel regions of the transistors are electrically connected to one another or to the substrate. In this case, charge carriers generated in the channel region can flow away, thereby avoiding what are referred to as floating body effects, such as, for example, an alteration of the threshold voltage of the transistor.
To that end, it is advantageous if, after the completion of the storage node,
Chen Kin-Chan
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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