Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
2001-03-01
2003-12-23
Loke, Steven (Department: 2811)
Semiconductor device manufacturing: process
Making passive device
C438S382000, C438S383000, C438S384000, C257S531000, C336S200000
Reexamination Certificate
active
06667217
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to integrate the fabrication of an inductor structure, and the fabrication of complimentary metal oxide semiconductor, (CMOS), devices.
(2) Description of Prior Art
Impedance matching is needed for radio frequency, (RF), integrated circuits. Inductor structures, comprised of conductive materials are sometimes used to provide the needed impedance matching function. A quality factor, or an inductance quality factor, of the inductor structure, is critical in determining the needed matching function for the integrated circuits. To satisfy process cost objectives, and to integrate with IF band circuit, the fabrication of the needed inductor is usually integrated into the fabrication process used to create the CMOS devices for integrated circuits, such as RF circuits.
This invention will describe a process for fabricating sub-micron, or sub-0.18 um, CMOS devices, in which the formation of the inductor structure is integrating into the CMOS fabrication process, featuring a thick, inductor structure, placed overlying a sub-metal layer. The thick, inductor layer, comprised of copper, is formed using only one additional photolithographic masking step, used to remove insulator layer from the top surface of the underlying sub-metal layer. A damascene process, used to form copper damascene structures, for the CMOS devices, also allows the formation of the thick copper inductor structure, in the opening exposing the sub-metal layer. The increased thickness of this copper layer results in an increased Q factor. Prior art, such as Yu et al, in U.S. Pat. No. 5,770,509, describe processes for forming inductor devices using substrate biasing procedures. That prior art however, does not describe the novel process sequence described in this present invention, in which a thick copper inductor structure, is formed simultaneously with adjacent CMOS devices, featuring the placement of the thick copper inductor structure, directly overlying a sub-metal layer, resulting in a inductor quality factor greater than the quality factor obtained from counterpart, thinner, inductor structures.
SUMMARY OF THE INVENTION
It is an object of this invention to integrate the formation of an inductor structure, into a fabrication process used to fabricate CMOS devices.
It is another object of this invention to form a copper inductor structure, using the same damascene, or a dual damascene process, used for fabrication of the CMOS metal interconnect structures.
It is yet another object of this invention to use one additional masking step, to form an opening in an insulator layer, to accommodate the copper inductor structure, overlaying and contacting, a sub-metal layer.
It is still yet another object of this invention to form a thick, copper inductor structure, to increase the Q, or quality factor of the copper inductor structure.
In accordance with the present invention a method of integrating the formation of a thick, dual damascene, copper inductor structure, with a high Q factor, into a fabrication process used to form sub-0.18 um, CMOS devices, is described, where the term 0.18 um refers to the channel length of an individual CMOS device. After formation of a sub-metal structure, used as a lower level, metal interconnect structure, for CMOS devices, an intermetal dielectric, (IMD), layer is deposited. A first opening is formed in the IMD layer, exposing a first portion of the sub-metal structure, in a region to be used for the copper inductor structure. Dual damascene openings are next formed in the same IMD layer, exposing second portions of the sub-metal layer, in a region to be used for the sub-0.18 um CMOS devices. A copper layer is next deposited, completely filling the first opening, and the dual damascene openings, followed by a chemical mechanical polishing procedure, resulting in copper, dual damascene structures, overlying and contacting the second portion of the sub-metal layer, and resulting in a copper inductor structure, located in the first opening in the IMD layer, overlaying and contacting the first portion of the sub-metal layer
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Chen Chun-Hon
Chung Jau-Yuann
Ho Yen-Shih
Hsu Heng-Ming
Ma Ssu-Pin
Ackerman Stephen B.
Gebremariam Samuel A
Loke Steven
Saile George O.
Taiwan Semiconductor Manufacturing Company
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