Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-11-06
2002-08-13
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000
Reexamination Certificate
active
06432795
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor manufacturing, and more particularly to a method of fabricating a cylindrical capacitor storage node having HSG silicon on inner walls of the cylindrical storage node.
2. Description of the Related Art
Recent advances in the scaling-down of integrated circuit devices have led to smaller wafer areas. High-density DRAM (dynamic random access memory) devices, for example, leave little room for a storage node of a memory cell. Yet even as the footprint (area of a silicon wafer allotted for individual memory cells) shrinks, the storage node must maintain a certain minimum charge storage capacity (cell capacitance), determined by design and operational parameters, to ensure reliable operation of the memory cell. Cell capacitance must be maintained at least 25 fF for preventing and limiting soft-error rate caused by alpha-particle interference and data-error rate caused by noise. It is thus increasingly important in the semiconductor integrated circuits industry of high-level integration that capacitors achieve a high charge storage per unit area of the wafer. For this reason, capacitor structures have become more and more complicated, from planar cell to trench cell or stack cell designs, and the CUB (capacitor under bit line) structure is being replaced by COB (capacitor over bit line) structure.
As is well known, cell capacitance may be represented by the following equation: C (capacitance)=&egr;×A/d, where &egr; is the dielectric constant of the capacitor dielectric, A is the electrode area and d represents the spacing between electrodes (thickness of the dielectric film). Accordingly, several techniques have been recently developed to increase the overall capacitance of the cell capacitor without significantly affecting the wafer area occupied by the cell. A first way is to use new materials having high dielectric constant. A second way is to form very thin dielectric films. A third way is to increase the effective surface area of the capacitor electrodes. However, application of high dielectric constant material as a dielectric film is still under study, and also has some problems associated with reliability. In addition, it is very difficult to form such thin dielectric films without reliability problems.
Accordingly, the third way is generally used to increase capacitance of the cell capacitor. To this end, three-dimensional capacitors such as stacked-type, cylindrical-type, trench-type, fin-type or the like, have been suggested to increase cell capacitance in a given cell area. Since both outer and inner surfaces can be utilized as an effective capacitor area, the cylindrical structure is favorably suitable for use as a three-dimensional capacitor, and is more particularly suitable for an integrated memory cell. Furthermore, new technologies have recently been developed for increasing the effective surface area by modifying the surface morphology of the polysilicon storage electrode itself, by engraving or controlling the nucleation and growth conditions of polysilicon. A hemispherical-grain (HSG) polysilicon layer can be deposited over a storage node to increase surface area and capacitance. However, as design rules have been scaled down to sub-quarter micron level, the possibility of an electrical bridge between adjacent storage nodes significantly increases when HSG silicon is grown on the outer surface of the cylindrical storage node.
To solve this problem associated with electrical bridges, a method for forming HSG silicon only on an inner surface of the cylindrical storage node has been suggested. Such method includes the step of forming HSG silicon on an inner surface of the cylindrical storage node, and then removing a sacrificial oxide layer to expose an outer surface of the storage node, by using wet chemicals. However, this method also has the problem associated with electrical bridges between adjacent storage nodes. In this case, the HSG silicon dislodges from the inner surface of the storage node during the step of removing the sacrificial oxide layer by wet etching, thereby causing an electrical bridge.
U.S. Pat. No. 5,892,702, the disclosure of which is incorporated herein by reference, discloses a method for fabricating a cylindrical capacitor having HSG on an inner surface of a storage node.
FIGS. 1A
to
1
J are cross-sectional views of a semiconductor substrate
10
, at selected stages of a cylindrical capacitor fabrication process in U.S. Pat. No. 5,892,702. Referring to
FIG. 1A
, an opening
49
is formed in a sacrificial oxide layer
48
. Thin second amorphous silicon layer
50
is formed in the opening
49
as shown in FIG.
1
B. Resist layer
51
is formed to fill the opening
49
as shown in
FIG. 1C. A
planarization process is carried out to separate the device by unit cell, down to the sacrificial oxide layer
48
, as shown in FIG.
1
D. Next, as shown in
FIGS. 1E and 1F
, the sacrificial oxide layer
48
and the underlying first amorphous silicon layer
47
a
are respectively removed to form space
260
having amorphous silicon sidewall
28
. The space
260
is filled with a spin-on-glass layer
52
as shown in FIG.
1
G. Next, the remainder of the resist layer
51
in the opening
49
is selectively removed, thereby forming a cylindrical storage node
26
electrically isolated by the spin-on-glass layer
52
from adjacent nodes
261
and
262
, as shown in FIG.
1
H. HSG silicon
41
is formed on inner surfaces of the storage node (i.e., the second amorphous silicon
50
) as shown in FIG.
11
. Thereafter, the spin-on-glass layer
52
is removed to expose outer surfaces of the storage node as shown in FIG.
1
J.
However, when the spin-on-glass layer
52
is removed in this fabrication process as described with respect to
FIG. 1J
, HSG silicon
41
formed on inner surfaces of the storage node can be dislodged therefrom, to cause electrical bridges between adjacent storage nodes. Accordingly, there is a strong need for a method of fabricating a capacitor storage node with high cell capacitance, but without electrical bridges between adjacent storage nodes.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a method of fabricating a cylindrical capacitor storage node having HSG silicon on inner walls thereof, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art. More particularly, the present invention is directed toward providing a method of fabricating a capacitor storage node having HSG silicon only on inner walls thereof, without electrical bridges between adjacent storage nodes.
It is a feature of the present invention that HSG silicon is formed only on inner walls of the storage node. It is another feature of the present invention that HSG silicon is formed after a sacrificial oxide layer is removed. It is still another feature of the present invention that the storage node is made of a double layer-structure, one layer defining the inner wall of the storage node and the other defining an outer wall of the storage node, where the other layer defining the outer wall of the storage node is made of a conductive layer that suppresses the growth of HSG silicon thereon. It is still another feature of the present invention that a cylindrical opening for a storage node can be formed with a sufficient photolithography process margin.
To achieve these objectives and features, and other features in accordance with a first embodiment of the present invention, there is provided a method of fabricating a capacitor storage node. The method includes providing a semiconductor substrate. A lower insulating layer, an etching stopper layer and an upper insulating layer are sequentially formed on the semiconductor substrate. Preferably, the etching stopper layer is made of a silicon nitride and the upper insulating layer is made of a silicon oxide. The stacked layers are patterned to form a storage opening to a predetermined portion of the semiconductor substrat
Nguyen Tuan H.
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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