Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1998-01-12
1999-06-15
Nguyen, Tuan H.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438255, 438396, H01L 2120
Patent
active
059131292
ABSTRACT:
A method of fabricating a capacitor structure for a dynamic random access memory. This method comprises the following steps: a transistor is provided on a semiconductor substrate, and spacers are formed over the sidewalls of a gate electrode of the transistor. A first oxide layer is formed over the transistor. A bit line is deposited to contact with the source region of the transistor. Thereafter, a second oxide layer is formed over the bit line. A contact opening is formed exposing the drain region. Then the hemispherical grained silicon layer is formed into the contact opening. A polysilicon layer is formed over the hemispherical grained silicon layer. Therefore both the hemispherical grained silicon layer and the third polysilicon layer have rough surfaces. Subsequent conventional processes for the complete formation of capacitor structure are performed. It is therefore the capacitor maintains a required capacitance while reducing the horizontal dimensions of the storage capacitor.
REFERENCES:
patent: 5354705 (1994-10-01), Mathews et al.
patent: 5760434 (1998-06-01), Zahurak et al.
patent: 5817555 (1998-10-01), Cho
patent: 5827766 (1998-10-01), Lou
Wang Chuan-Fu
Wu Der-Yuan
Nguyen Tuan H.
United Microelectronics Corp.
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