Method of fabricating a bit line of flash memory

Details Method of fabricating a bit line of flash memory Method of fabricating a bit line of flash memory

1999-11-05

2001-04-10

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000

Reexamination Certificate

active

06214741

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for fabricating a flash memory, and more particularly, to a method for fabricating a split-gate flash memory.
2. Description of the Related Art
At present, nonvolatile memory is widely used in the whole range of electrical devices. In particular, programmable nonvolatile memory having a flash memory structure such as the erasable programmable read-only memory (EPROM) and the electrically erased programmable read-only memory (EEPROM) has attracted immense interest. In general, a flash memory comprises two gates, a floating gate for charge storage and a control gate for data accessing. The floating gate is in a floating state without being connected to any electrical circuit and is located between the control gate and a substrate while the control gate is connected to a word line.
FIGS. 1A-1C
are schematic, cross-sectional views illustrating fabrication of a split-gate flash memory.
Referring to
FIG. 1A
, a patterned oxide layer
102
is formed on a silicon substrate
100
to serve as a mask layer. The oxide layer
102
has an opening
104
for fabricating a bit line.
Referring to
FIG. 1B
, an ion implanting process is performed. Ions are implanted into the exposed portions of the silicon substrate
100
to form bit lines
106
and
108
, wherein the bit line
106
serves as a source and the bit line
108
serves as a drain.
Referring to
FIG. 1C
, after the oxide layer
102
is removed, a tunneling oxide layer
110
is formed over the whole substrate
100
. A polysilicon floating gate
112
is formed above a portion of the drain
108
and above the portion of the substrate
100
beside the drain
108
. A split-gate oxide
114
is then formed over the substrate
100
. A control gate
116
connected to a word line is formed above portions of the floating gate
112
and the drain
106
and above the portion of the substrate therebetween.
As the integration of integrated circuit (IC) is increased, the width of bit line in the flash memory is narrowed. It is well known in the art that the cross-sectional area of the bit line is decreased with the line width and results in an increase of the resistance, thereby reducing the speed of device operation. Although the resistance of a bit line in the prior art can be reduced by increasing the doped ion concentration of the bit line, the junction breakdown voltage and the carrier punchthrough capability in the flash memory are relatively degraded and therefore affect the operation characteristic of the device. In addition, after a thermocycle in the back-end process, the ions implanted into the bit line will diffuse out into adjacent regions and cause a subthreshold leakage.
The doped ion concentration of the bit line should be increased because of the shrinkage of the line width, but it should be decreased since the degradation of the junction breakdown voltage and carrier punchthrough capability. Hence, the process window is greatly shrunk, which increases the process difficulty and reduces the quality of the product.
SUMMARY OF THE INVENTION
The present invention therefore provides an improved method of fabricating a bit line of a flash memory within two different doped ion concentrations in a SOI substrate, and thereby forming a narrow bit line without increasing the resistance of the bit line and without the problems of the junction breakdown voltage, carrier punchthrough capability, diffusion, etc.
The invention provides a method of fabricating a bit line of a flash memory. The method of the invention comprises the following steps. A silicon-on-insulator (SOI) substrate is provided. The substrate comprises a buried oxide layer and a silicon layer thereon. A patterned hard mask layer is formed on the silicon layer. The exposed silicon layer and buried oxide layer thereunder are removed to form a bit line opening while using the hard mask layer as a mask. A conformal lightly doped polysilicon layer is formed over the substrate. A heavily doped polysilicon layer is formed over the substrate and filling the bit line opening. The lightly doped and heavily doped polysilicon layers are removed until arriving at the silicon layer to form a bit line. The hard mask layer is then removed.
According to the method of the invention, a polysilicon bit line with two different doped ion concentrations is formed. The internal portion of the bit line with a heavily doped ion concentration can reduce the resistance, and the external portion of the bit line with a lightly doped ion concentration can avoid the problems of junction breakdown voltage, carrier punchthrough capability, diffusion, etc.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5925575 (1999-07-01), Tao et al.
patent: 6069091 (2000-05-01), Chang et al.

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