Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Self-aligned
Reexamination Certificate
2001-06-15
2002-06-04
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Self-aligned
Reexamination Certificate
active
06399455
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of integrated circuit structures and, in particular, to the fabrication of an ultra-small, sub-lithographic bipolar transistor emitter using conventional lithography techniques.
2. Discussion of the Related Art
A bipolar transistor is a three-terminal device that can, when properly biased, controllably vary the magnitude of the current that flows between two of the transistor's terminals. The three terminals include a base terminal, a collector terminal and an emitter terminal. The charge carriers, which form the current, flow between the collector terminal and the emitter terminal; variations in the voltage applied to the base terminal cause the magnitude of the current to vary.
Due to the increasing demand for battery-powered devices, there is a need for a bipolar transistor that utilizes less power. Lower power consumption can be obtained in a bipolar transistor by reducing the maximum current that can flow between the collector and emitter terminals. One approach for reducing the maximum current is to reduce the size of the base-to-emitter junction, preferably to sub-lithographic feature sizes.
The literature reports a method that allows the formation of polysilicon ridge emitter transistors down to 0.1 micron width without relying on advanced lithography tools. See “Poly Emitter Transistor (PRET): Simple Low Power Option to a Bipolar Process”, by Wim van der Wel, et al., IEDM 93-453, 1993, pp. 17.6.1-17.6.4. However, this method utilizes two polysilicon layers, as shown in the
FIGS. 1A-1C
fabrication sequence.
As shown in
FIG. 1A
, the van der Wel et al. technique begins in the conventional manner with an integrated circuit structure that includes a trench isolation structure
100
formed in a semiconductor substrate to define a substrate active device region
102
. An n-type collector region
104
is formed in the substrate active device region
102
and a p-type base region
106
is formed above the collector region
104
. A layer of silicon dioxide
108
is formed to extend over the active device region
102
. A first layer of n-doped polysilicon is then formed over the layer of dielectric material
108
. The polysilicon layer and the underlying silicon dioxide
108
are then patterned to define a poly
1
emitter region
110
that extends over the p-type base region
106
but is separated from the base region
106
by intervening dielectric material
108
. A second layer of n-doped polysilicon is then formed over the above-described structure, as further shown in FIG.
1
A.
As shown in
FIG. 1B
, the poly
2
layer is then anisotropically etched to define poly
2
sidewalls
112
on the poly
1
emitter region
110
. An subsequent annealing step results in diffusion of n-type dopant from the poly
2
sidewall formed on the base region
106
into the p-type base region
106
to define an n-type emitter junction
114
in the base region
106
. Dielectric sidewalls
116
are then formed to electrically isolate the poly
2
sidewalls. Finally, salicide films
118
are formed on the base region
106
and on the poly
1
emitter region
110
, as shown in FIG.
1
C.
Although the van der Wel technique described above results in small emitters, it has the following disadvantages. First, the slope of the poly
1
emitter region is critical to success of this method; the slope could affect the width of the emitter (i.e. the poly
2
sidewalls) significantly, introduce large variability in the emitter width across the wafer and, therefore, result in performance variability. Second, the possible large variability of the poly emitter ridge, i.e. the poly
2
, could in turn introduce large variability in the oxide spacers, which could cause shorts between the emitter and the base regions during the salicidation step. Third, emitter n-type dopant diffusion is less in the structure, compared to conventional single poly device architectures, due to the possible presence of a poly
1
/poly
2
interfacial barrier in the emitter structure, as shown in FIG.
1
C.
Thus, there is a need for a low-power bipolar transistor with a sub-lithographic base-to-emitter junction that reduces, or preferably eliminates, the previously-described drawbacks.
SUMMARY OF THE INVENTION
The present invention provides a bipolar transistor structure with an ultra-small polysilicon emitter and a method of fabricating the structure. The bipolar transistor structure includes trench isolation formed in a semiconductor substrate to define a substrate active device region. A collector region having a first conductivity type is formed conventionally beneath the surface of the substrate active device region. A base region having a second conductivity type opposite the first conductivity type is formed conventionally in the substrate active device region above the collector region and extending to the surface of the substrate active device region. A layer of dielectric material is formed to extend at least partially over the surface of the base region. A layer of polysilicon, doped to the first conductivity type, is then formed over the surface of the layer of dielectric material and extending over the edge of the layer of dielectric material and over the surface of the base region. A chemical mechanical polishing step is then performed to planarize the layer of doped polysilicon. The layer of doped polysilicon is then patterned to define a polysilicon emitter region that extends over the edge of the layer of dielectric material to provide an ultra-small, sub 0.2 micron, polysilicon emitter contact on the surface of the base region. The polysilicon emitter region is then heated such that dopant diffuses from the polysilicon emitter contact through the surface of the base region to form an emitter junction region having the first conductivity type at the surface of the base region beneath the polysilicon emitter contact. Dielectric sidewall spacers are then formed on the sidewalls of the polysilicon emitter region to electrically isolate the polysilicon emitter sidewalls.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings that set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 5061644 (1991-10-01), Yue et al.
patent: 5086016 (1992-02-01), Brodsky et al.
patent: 6001701 (1999-12-01), Carroll et al.
patent: 6124180 (2000-09-01), Chambers et al.
Wim van der Wel, et al. “Poly-Ridge Emitter Transistor (PRET): Simple Low-Power Option to a Bipolar Process”, IEDM 93-453, IEEE 1993.
Fourson George
National Semiconductor Corporation
Stallman & Pollack LLP
LandOfFree
Method of fabricating a bipolar transistor with ultra small... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating a bipolar transistor with ultra small..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating a bipolar transistor with ultra small... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2945256