Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
1999-12-02
2002-10-22
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S109000, C438S126000, C438S127000
Reexamination Certificate
active
06468834
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in die-up ball grid array BGA packages for integrated circuits.
2. Prior Art
FIG. 1
illustrates a conventional die-up fine pitch ball grid array FPBGA package
50
in which an integrated-circuit die
52
is adhesively mounted to a top surface of a flexible, insulated polyimide tape
54
. Bonding wires
56
are connected between wire-bonding pads on a top surface of the integrated-circuit die
52
and wire-bonding sites
58
on the top surface of the insulated polyimide tape layer
54
. The integrated-circuit die, the bonding wires, and the conductive bonding sites on the top side of the insulated tape layer are all encapsulated in an encapsulation cap
60
.
Conductive tras are formed on the top surface of the insulated polyimide tape. The conductive traces provide connections between the wire-bonding sites
58
and a number of solder-ball mounting areas, typically shown as
62
, which are also formed on the top side of the insulated polyimide tape. A number of holes, typically shown as
64
, are formed through the insulated polyimide tape layer to expose the bottom sides of the solder-ball mounting areas
62
on the top side of the insulated polyimide tape. The holes allow solder balls, typically shown as
66
, to be attached through the holes in the insulated polyimide tape to the solder-ball mounting areas on the top side of the insulated polyimide tape.
The solder-ball mounting areas are arranged in a grid pattern. In order to mount an HBGA package to the surface of a printed-circuit board, the grid pattern of the solder balls is placed over a corresponding grid pattern of solderable areas on the printed-circuit board. The solder balls are then heated to a temperature sufficient to melt the solder balls and to solder the BGA package to the surface of the printed-circuit board.
The insulated polyimide tape layer of a conventional die-up BGA package is good for routing of conductive traces but is limited when solder ball pads are to be attached to the tapes because the conductive traces have to go around the solder ball pads which interfere with routing of the conductive traces on the insulated tape layer. A Problem with a conventional die-up BGA package, which uses an insulated polyimide tape layer, is that, particularly for large body sizes, warpage can occur due to the thinness and softness of the tape.
SUMMARY OF THE INVENTION
The invention provides a solution to the routing problems by combining an insulated tape layer with circuit board technology. This approach keeps costs down and depends only on well-developed via technology for printed circuit boards while leaving the routing of conductive traces to tape technology.
A die-up BGA package for an integrated-circuit die includes a rigid circuit board having a plurality of electrically conductive plated-through holes formed therethrough where each of the plated-through holes has a top surface and a bottom surface. An integrated-circuit die has a bottom die-mounting surface which is mounted to the top surface of the rigid circuit board.
A flexible insulated tape layer has a lower surface fixed to the upper surface of the rigid circuit board. A central opening is formed in the tape layer to accommodate mounting of the integrated-circuit die to the upper surface of the rigid circuit board. The upper surface of the flexible insulated tape layer has a number of wire-bonding sites formed thereupon and the lower surface of the flexible insulated tape layer has a number of contact areas formed thereupon.
Means are provided for electrically connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Such connection means include vias formed through the flexible insulated layer and filled with conductive material such as solder. Conductive traces are formed on the upper surface of the flexible insulated tape layer for the connecting wire-bonding sites formed on the upper surface to the conductive vias. Such conductive means alternatively includes plated-through holes.
Bonding-wire loops are connected between wire-bonding pads formed on the integrated-circuit die and wire-bonding sites on the upper surface of the flexible insulated tape layer.
Means are provided for connecting the top and bottom surfaces of the rigid circuit board, including vias filled with solder and plated-through holes. The solder balls are connected to the lower surface of the plated-through holes or conductive vias. An encapsulation layer covers the integrated-circuit die and the bonding wires.
For the die-up configuration, the flexible insulated tape is supported by the rigid circuit board and the plated through holes provide connections for the solder balls on the bottom side of the rigid circuit board to the contact areas on the flexible insulated tape which are located adjacent the top side of the rigid circuit board.
Die-up HBGA packages produced according to the present invention have the advantage that no large openings are required through the insulated tape layer to allow solder balls to extend through such openings to contact areas on the top surface of the insulated tape layer. HBGA packages produced according to the present invention have another advantage that routing of conductive traces on the top side of the insulated tape layer is easier because the solder balls contact vias in the insulated tape layer. HBGA packages produced according to the present invention also have the advantage that existing via fabrication techniques can be used to form vias in the insulated tape layer. HBGA packages produced according to the present invention also have the advantage that the circuit boards have only vias and no etched conductors so that they can be produced relatively inexpensively.
REFERENCES:
patent: 5404044 (1995-04-01), Booth et al.
patent: 5477082 (1995-12-01), Buckley, III et al.
patent: 5530288 (1996-06-01), Stone
patent: 5640051 (1997-06-01), Tomura et al.
patent: 5659952 (1997-08-01), Kovac et al.
patent: 5763939 (1998-06-01), Yamashita
patent: 5783865 (1998-07-01), Highashiguchi et al.
patent: 5909058 (1999-06-01), Yano et al.
patent: 5999415 (1999-12-01), Hamzehdoost
patent: 6069407 (2000-05-01), Hamzehdoost
patent: 3-71648 (1991-03-01), None
patent: 6-291165 (1994-10-01), None
Chambliss Alonzo
Chaudhuri Olik
LandOfFree
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