Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1997-07-16
2000-10-03
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
716 11, G06F 1750
Patent
active
061287687
ABSTRACT:
A layout parasitic extraction system is disclosed. The present invention is a connectivity-based approach for extracting layout parasitics. The present invention creates a connectivity-based database, where geometries of a layout are organized by net. The present invention allows net-by-net extraction of layout parasitics using a connectivity-based database. Furthermore, a user can select a net or nets for extraction. The present invention outputs a database containing nets and their extracted layout parasitics. The present invention can create a netlist format file from a database containing nets and their extracted parasitics to allow back annotation of layout parasitics into a circuit schematic or for use for other software (possibly from a third-party).
REFERENCES:
patent: 4837447 (1989-06-01), Pierce et al.
patent: 5031111 (1991-07-01), Chao et al.
patent: 5043920 (1991-08-01), Malm et al.
patent: 5050091 (1991-09-01), Rubbin
patent: 5051938 (1991-09-01), Hyduke
patent: 5081602 (1992-01-01), Glover
patent: 5157668 (1992-10-01), Buenzli, JR. et al.
patent: 5202841 (1993-04-01), Tani
patent: 5210701 (1993-05-01), Hana et al.
patent: 5218551 (1993-06-01), Agawal et al.
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5247456 (1993-09-01), Ohe et al.
patent: 5278105 (1993-01-01), Eden et al.
patent: 5278769 (1994-01-01), Bair et al.
patent: 5299139 (1994-03-01), Baisuck et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5305229 (1994-04-01), Dhar
patent: 5351197 (1994-09-01), Upton et al.
patent: 5359584 (1994-10-01), Fukushima et al.
patent: 5367468 (1994-11-01), Fukasawa et al.
patent: 5381345 (1995-01-01), Takegami et al.
patent: 5392222 (1995-02-01), Noble
patent: 5402357 (1995-03-01), Schaefer et al.
patent: 5402358 (1995-03-01), Smith et al.
patent: 5416717 (1995-05-01), Miyama et al.
patent: 5440720 (1995-08-01), Baisuck et al.
patent: 5452224 (1995-09-01), Smith, Jr. et al.
patent: 5459673 (1995-10-01), Carmean et al.
patent: 5461579 (1995-10-01), Misheloff et al.
patent: 5463563 (1995-10-01), Bair et al.
patent: 5490095 (1996-02-01), Shimada et al.
patent: 5610832 (1997-03-01), Wikle et al.
patent: 5706477 (1998-01-01), Goto
patent: 5787268 (1998-07-01), Sugiyama et al.
patent: 5828580 (1999-10-01), Ho
patent: 5903469 (1999-05-01), Ho
Chang, E. et al., "Using a Statistical Metrology Framework to Identify Systematic and Random Sources of Die- and Wafer-level ILD Thickness Variation in CMP Processes," IEEE, 1995, pp. 499-502.
Chang, Keh-Jeng et al., "HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs," IEEE, 1991, pp. 294-297.
Chang, Keh-Jeng et al., "Parameterized SPICE Subcircuits for Multilevel Interconnect Modeling and Simulation," IEEE 1992 pp. 779-789.
Chang, Keh-Jeng et al., "Nondestructive Multilevel Interconnect Parameter Characterization for High-Performance Manufacturable VLSI Technologies," 1993 Symposium on VLSI Technology Digest of Technical Papers, May 17-19, 1993, The Japan Society of Applied Physics, The IEEE Electron Devices Society, pp. 135-136.
Schwartz, Geraldine Cogin et al., "TXRF Surface Impurity Comparison of t-DCE and TCA Oxidation," Journal of Electrochem. Soc., vol. 139, No. 12, Dec. 1992, pp.L118-L121.
Yu, Crid et al., "Use of Short-Loop Electrical Measurements for Yield Improvement," IEEE Transactions On Semiconductor Manufacturing, vol. 8, No. 2, May, 1995, pp. 150-159.
Rugen et al "An Interactive Layout Design System With Real-Time Logical Verification and Extraction of Layout Parasitics," IEEE, pp. 698-704, Jun. 1988.
Chang et al "HIVE: An Express and Accurate Interconect Capacitance Extrctor for Submicron Multilevel Conductor Systems," IEEE, pp. 359-363, 1991.
W. Meier "Hierachical Layout Verification for Submicron Designs," IEEE, pp. 382-386, 1990.
Yehuda Shiran "YNCCdb: A New Database Representation FOF VLSI Circuits for Fast Navigation and Layout Verification Applications," IEEE, pp. 150-155, 1988.
Belkale, K.P. et al., "Parallel Algorithms for VLSI Circuit Extraction," IEEE Trans. on CAD of Integrated Cir. & Systems, vol. 10, No. 5, May 1991, pp. 604-618.
Chiang, Kuang-Wei, "Resistance Extraction and Resistance Calculation of GOALIE2," Proc. of the Design Auto. Conf., Las Vegas, Jun. 25-29, 1989, Paper 40.3, pp. 682-685.
Ladage, L. et al., "Resistance Extraction and Along the Current Flow," Proc. of the Custom Integrated Circuits Conf., San Diego, May 9-12, 1993, pp. 17.5.1-17.5.4.
Marple, David et al, "Tailor: A Layout System Based on Trapezoidal Corner Stiching," IEEE Trans. on Computer-Aided-Design of Int. Cir. and Sys., vol. 9, No. 1, Jan. 1990, pp. 66-90.
Ramkumar, Balkrishna et al., "ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD," IEEE Trans. on Computer-Aided Design of Int. Cir. and Sys., vol. 13, No. 7, Jul. 1994, pp. 829-842.
Rugen, Irmtraud et al., "An Interactive Layout Design System with Real-Time Logical Verification and Extraction of Layout Parasitics," IEEE Jor. of Solid-State Circuits, vol. 23, No. 3, Jun. 1988, pp. 66-90.
Wang, Z. and Quiming Wu, IEEE Transactions on Computer-Aided Design, vol. 11, No. 4, Apr. 1992, "A Two-Dimensional Resistance Simulator Using the Boundary Element Method", pp. 497-504.
Fukuda, Sanae et al., IEEE Transactions on Computer-Aided Design, vol. 9, No. 1, Jan. 1990, "A ULSI 2-D Capacitance Simulator for Complex Structures Based on Actual Processes", pp. 39-47.
McCormick, Steven P., 21st Design Automation Conference, Paper 39.2, "EXCL: A Circuit Extractor for IC Designs", pp. 616-623 (1984).
Stark, Don and Mark Horowitz, 24th ACM/IEEE Design Automation Conference, Paper 32.2, "REDS: Resistance Extraction for Digital Simulation", pp. 570-573 (1987).
Horowitz, Mark and Robert W. Dutton, IEEE Transactions on Computer-Aided Design, vol. CAD-2, No. 3, Jul. 1983, "Resistance Extraction from Mask Layout Data", pp. 145-150.
Hwang, Jerry P., 28th ACM/IEEE Design Automation Conference, Paper 41.1, "REX--A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis", pp. 717-722 (1991).
Lintz Paul R.
Siek Vuthe
Synopsys Inc.
LandOfFree
Method of extracting layout parasitics for nets of an integrated does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of extracting layout parasitics for nets of an integrated, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of extracting layout parasitics for nets of an integrated will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-206064