Method of expanding bus loading capacity

Details Method of expanding bus loading capacity Method of expanding bus loading capacity

1997-10-01

2001-02-27

Lee, Thomas C. (Department: 2782)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S008000, C710S010000, C713S001000, C713S002000

Reexamination Certificate

active

06195717

ABSTRACT:

APPENDICES
Appendix A, which forms a part of this disclosure, is a list of commonly owned copending U.S. patent applications. Each one of the applications listed in Appendix A is hereby incorporated herein in its entirety by reference thereto.
Appendix B, which forms part of this disclosure, is a copy of the U.S. provisional patent application filed May 13, 1997, entitled “ISOLATED INTERRUPT STRUCTURE FOR INPUT/OUTPUT ARCHITECTURE” and assigned application Ser. No. 60/047,003. Page 1, line 17 of the provisional application has been changed from the original to positively recite that the entire provisional application, including the attached documents, forms part of this disclosure.
Appendix C, which forms part of this disclosure, is a copy of the U.S. provisional patent application filed May 13, 1997, entitled “THREE BUS SERVER ARCHITECTURE WITH A LEGACY PCI BUS AND MIRRORED I/O PCI BUSES” and assigned application Ser. No. 60/046,490. Page 1, line 15 of the provisional application has been changed from the original to positively recite that the entire provisional application, including the attached documents, forms part of this disclosure.
COPYRIGHT RIGHTS
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to information processing systems, such as computer servers and personal computers (PCs). More particularly, this invention relates to the transfer of control and data signals within an information processing system having multiple bus architecture.
2. Description of the Related Art
Information processing systems, such as personal computers (PCs), have virtually become an inseparable part of everyone's daily activities. These systems process an enormous amount of information in a relatively short time. To perform these sophisticated tasks, the computer system typically includes a microprocessor, memory modules, various system and bus control units, and a wide variety of data input/output (I/O) and storage devices. These computer components communicate information using various data rates and protocols over multiple system buses. The demand for faster processing speeds, and the revolutionary fast-track development of computer systems, have necessitated the use of interconnecting devices. These devices act as bridges among various data transfer protocol within the computer system. One example of such interconnecting devices is the peripheral component interconnect (PCI) bridge.
The PCI Local Bus Specification, Revision 2.1 (“PCI Specification”) defines a PCI Local Bus with the primary goal of establishing an industry standard. The PCI Local Bus is a 32-bit or 64-bit bus with multiplexed address and data lines. The bus is intended for use as an interconnect mechanism between highly integrated peripheral controller components, peripheral add-in boards, and processor/memory systems. The PCI Specification includes the protocol, electrical, mechanical, and configuration specification for PCI Local Bus components and expansion boards. The electrical definition provides for 5.0 V (e.g., desktop PCs) and 3.3 V (e.g., mobile PCs) signaling environments.
Typical PCI Local Bus implementations support up to four add-in boards. An add-in board is a circuit board that plugs into a motherboard and provides added functionality. The motherboard is the main circuit board which contains the basic function (e.g., a central processing unit or CPU, I/O, and expansion connectors) of a computer system.
FIG. 1
shows a typical PCI Local Bus system architecture. As shown in
FIG. 1
, a processor
102
, a cache
104
, and a dynamic random access memory (DRAM)
106
are connected to a PCI Local Bus
112
through a PCI Bridge
108
. The PCI Bridge
108
provides the logic that connects one bus to another to allow an agent (i.e., an entity that operates on a computer bus) on one bus to access an agent on the other. The PCI Bridge
108
provides a low latency path through which the processor
102
, the cache
104
, and DRAM
106
may directly access PCI devices mapped anywhere in the memory or I/O address spaces. Typical PCI devices include an audio card
116
, a motion video card
120
, a local area network (LAN) interface
124
, a small computer system interface (SCSI)
128
, an expansion bus interface
132
, and a graphics card
136
. The expansion bus interface
132
typically connects industry standard architecture (ISA) and extended ISA (EISA) devices (not shown in this figure) to the PCI local bus
112
via an ISA, EISA, or MicroChannel
140
. The expansion bus interface
132
is often referred to as the ISA/EISA bridge.
PCI bus drivers spend a relatively large portion of time in transient switching. PCI bus drivers are specified in terms of their AC switching characteristics. Specifically, the voltage to current relationship (V/I curve) of the driver through its active switching range is the primary means of specification. The PCI Specification defines that PCI bus drivers achieve acceptable AC switching behavior in typical configurations of six loads on the motherboard and two expansion connectors (each is considered as two loads). The PCI bus drivers can also achieve acceptable switching behavior in configurations of two loads on the mother board and four expansion connectors. Hence, the loading capacity on the PCI Local Bus
112
is limited to ten loads. In practice, however, a standard PCI configuration uses a Processor-to-PCI bridge to generate the PCI bus with up to four card slots thereon. Violation of expansion board trace length or loading limits may compromise system signal integrity.
The foregoing loading limits have imposed serious restrictions on system designers, and prevented the addition of new functions to computer systems. Several attempts have been made to increase the loading capacity of a PCI bus. One approach involves implementing a Processor-to-PCI bridge by coupling it to a local processor bus (i.e., the bus to which the CPU is connected). The Processor-to-PCI bridge provides a connection between the local processor bus and a PCI bus. As noted above, the loading capacity of such a PCI Chipset bridge, however, is limited to four card slots. With the increasing performance demands on personal computers, such load capacity remains insufficient. Accordingly, there is a need in the technology to expand the loading capacity of a PCI bus. Such expansion of loading capacity will ensure the demands of adding powerful features to already overburdened information processing systems can be met.
SUMMARY OF THE INVENTION
To overcome the limitations of the related art, the invention provides a method for expanding the loading capacity of a PCI bus beyond its maximum loading capacity. The invention fully complies with the PCI Specification and does not compromise the system signal integrity.
According to one embodiment of the invention, a PCI bridge system for expanding the loading capacity of a PCI bus is provided. The PCI bridge system allows the expansion of the loading capacity of a PCI bus up to sixteen add-in board connectors (“card slots”). In this embodiment, a first-to-second bridge (e.g., the “processor-to-PCI bridge”) connects a local processor bus to four second-to-third bridges (e.g., the “PCI-to-PCI bridges”). Each PCI-to-PCI bridge supports up to four PCI card slots via its unique PCI bus. Hence, the PCI bridge system results in expanding the PCI bus to sixteen card slots without violating the loading capacity or signal integrity of the system.
In another embodiment of the invention, two or more processor-to-PCI bridges are integrated with the local processor bus. Each processor-to-PCI bridge connects the local processor bus to four PCI-to-PCI bridges via its unique PCI bus.

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