Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-05-14
2001-04-17
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S721000
Reexamination Certificate
active
06219806
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of executing test programs for a semiconductor testing system for performing a variety of function tests on a semiconductor memory or other components.
2. Description of the Related Art
Hitherto known as such semiconductor testing system for running various function tests on the semiconductor memory are ones of two types, that is, per-pin type and shared resource type. The per-pin type semiconductor testing system enables a timing edge defining a switching timing of pattern data or the like to be set for each pin (terminal) of the semiconductor memory to be tested, advantageously making it possible to provide fine settings for the function tests. More specifically, it comprises a timing generator including the same number of timing edge generating circuits as pins of the semiconductor memory, with each timing edge generating circuit capable of generating an arbitrary timing edge.
The shared resource type semiconductor testing system on the other hand has a plurality of timing edges shared by all the pins so that the hardware is conveniently simplified although the reduced degree of freedom in the setting of the timing edge. More specifically, its timing generator includes a timing edge generating circuit common to the pins of the semiconductor memory so that any one is selected for the correlation with the respective pins from among a plurality of (e.g., eight different) timing edges provided by the timing edge generating circuit. Thus, any one is selected from among the eight different timing edges provided by the timing edge generating circuit so as to allow individual correspondence with each pin of the semiconductor memory.
Incidentally, the above per-pin type and shared resource type semiconductor testing systems are both computer controlled and include a processing unit called a tester processor for executing a predetermined test program to run a variety of function tests on the semiconductor memory. Although the test program is generally executed by a predetermined operating system (OS), the per-pin type semiconductor testing system and the shared resource type semiconductor testing system have different operative procedures effected by the tester processor upon the execution of the test program, due to the difference in the timing edge generating mechanisms or the like. For this reason, use must be made of different operating systems depending on whether the semiconductor testing system is of the per-pin type or of the shared resource type, preventing the operating system from being shared.
For example, as described hereinabove, the timing generator contained in the shared resource type semiconductor testing system is provided with a common timing edge generating circuit corresponding to the pins of the semiconductor memory. The instant that the execution is made of a statement of the test program describing values of a plurality of timing edges (e.g., ACLK1, ACLK2, etc.) set by the timing edge generating circuit, corresponding values of the timing edges are set to the timing edge generating circuit.
On the contrary, the timing generator included in the per-pin type semiconductor testing system is provided with a plurality of timing edge generating circuits having one-to-one correspondence with each pin of the semiconductor memory. The timing edge generating circuits are set independently of each other, and the actual setting is performed immediately before the execution of measurement of the output value from the semiconductor memory.
In this manner, regardless of the common test program, the operating system for use in the conventional semiconductor testing system must allow the tester processor to act differently depending on whether the operating system is applied to the per-pin type semiconductor testing system or the shared resource type semiconductor testing system, with the result that there arises a necessity to develop one having different specifications each time, resulting in laborious development of the operating systems.
In addition, the use of different operating systems leads to the tester processor effecting different operative procedures, which means that the function tests are run under different test conditions in the strict sense of the word. Thus, in order to ensure that the function tests are at all times run under the same conditions, it is preferred that the same operative procedure be effected by the tester processor by sharing a single operating system.
It is therefore the object of the present invention to provide a method of executing a test program for a semiconductor testing system, ensuring the same operative procedure upon the execution of a test program irrespective of the type of the semiconductor testing system.
SUMMARY OF THE INVENTION
In a preferred embodiment, a method of executing a test program for a semiconductor testing system of the present invention comprises the steps of, upon the execution of a statement of the test program designating a predetermined set value required for the run of the function test, storing thus designated set value in a predetermined data area; and upon the execution of a statement of the test program providing an instruction on the run of the function test, reading the set value stored in the data area and performing the setting of a corresponding circuit, after which the function test is run.
Even when the function test is performed using the shared resource type semiconductor testing system, there is no need to immediately set a corresponding circuit upon the execution of the statement designating a set value necessary for the run of the function test, thereby making it possible to share the operative procedure upon the execution of the test program with the per-pin type semiconductor testing system.
REFERENCES:
patent: 4736375 (1988-04-01), Tannhauser et al.
patent: 5432942 (1995-07-01), Trainer
patent: 5544175 (1996-08-01), Posse
Advantest Corporation
Chung Phung M.
Dellett and Walters
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