Method of executing coded instructions in a multiprocessor havin

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711118, 711130, 711148, 711169, 712 10, 712 16, 712 32, G06F 930

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active

060353740

ABSTRACT:
A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

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Greenley et al, "UltraSPARC: the next generation superscalar 64-bit SPARC", cOMPCON '95 `Technologies for the information Superhighway`, Digest of Papers., pp. 442-449, Mar. 5, 1995.

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