Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-06-25
2000-03-07
An, Meng-At T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711118, 711130, 711148, 711169, 712 10, 712 16, 712 32, G06F 930
Patent
active
060353740
ABSTRACT:
A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.
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Chamdani Joseph I.
Panwar Ramesh
An Meng-At T.
Kubida William J.
Langley Stuart T.
Sun Microsystems Inc.
Whitmore Stacy
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