Method of evaluating signal propagation delay in logic integrate

Details Method of evaluating signal propagation delay in logic integrate Method of evaluating signal propagation delay in logic integrate

1996-04-26

1998-06-02

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

057610819

ABSTRACT:
Signal propagation delay in an inverter chain having a first inverter cell and a second inverter cell connected by an intercell wire, is evaluated. In order to guarantee that a first inverter cell delay is always evaluated to be positive (A) a logic threshold voltage for an increase in input pin voltage of the first inverter cell is set to a voltage below a switching threshold voltage of the first inverter cell, and (B) a logic threshold voltage for a decrease in input pin voltage of the first inverter cell is set to a voltage above the switching threshold voltage of the first inverter cell. Similarly, logic threshold voltages for an increase and a decrease in input pin voltage of the second inverter cell are determined. Additionally, in order to guarantee that an intercell wire delay is always evaluated to be positive, logic threshold voltages for an output pin voltage of the first inverter cell are made to agree with the logic threshold voltages for the input pin voltage of the second inverter cell.

REFERENCES:
patent: 5239481 (1993-08-01), Brooks et al.
patent: 5274568 (1993-12-01), Blinne et al.
patent: 5359535 (1994-10-01), Djaja et al.
patent: 5471409 (1995-11-01), Tani
patent: 5548526 (1996-08-01), Misheloff
patent: 5559715 (1996-09-01), Misheloff

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