Method of etching shaped features on a substrate

Details Method of etching shaped features on a substrate Method of etching shaped features on a substrate

2002-10-01

2004-08-31

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S714000, C438S735000

Reexamination Certificate

active

06784110

ABSTRACT:

BACKGROUND
The present invention relates to a method of etching shaped features on a substrate.
In substrate fabrication, for example, in the fabrication of integrated circuit chips on a substrate of silicon or compound semiconductor, or in the fabrication of displays, one or more layers of semiconducting, dielectric, and conducting materials are formed on the substrate and the layers are then etched to form a pattern of features on the substrate comprising, for example, gates, vias, contact holes, trenches, and/or interconnect lines. For example, one or more layers of dielectric and semiconducting material may be formed on the substrate and etched to form a pattern of features comprising raised structures, such as for example raised spacer structures between gates. The layers may be etched by providing an energized process gas to etch the substrate. The process gas may be energized to etch the substrate by RF or microwave power.
However, it is often difficult to etch features on the substrate having a desired dimension, such as a predetermined height, width or profile, or a desired shape, such as a wineglass, square, or rectangular shape. Overetching or underetching of features can cause undesirable dimensions and shapes. As an example, it can often be difficult to etch a raised feature to provide a structure having square shoulders or corners. Excessive etching of the sidewalls of the feature can erode the corners of the feature and result in rounded corners. Overetching of the sidewalls may also result in an undesirable reduction in the feature width. The rounded corners and reduction in the width of the feature can adversely affect subsequent process steps and the performance of the final integrated circuit structure.
Thus, it is desirable to etch a feature to a desired dimension or feature shape. It is further desirable to etch a feature without overetching of the sidewalls of the feature or loss of dimension of the feature.
SUMMARY
A substrate etching method comprising:
(a) providing a substrate in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor;
(b) in a first stage, providing in the process zone, an energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor; and
©) in a second stage, providing in the process zone, an energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.
A method of etching a substrate in a substrate processing chamber comprising an antenna and process electrodes, the method comprising:
(a) providing a substrate in the chamber, the substrate having a pattern of features, the features comprising a semiconductor mesa with a dielectric sidewall;
(b) in a first plasma stage, providing a first etching gas in the chamber and applying a first bias RF power level to the process electrodes and a first source RF power level to the antenna, thereby energizing the first etching gas to etch the semiconductor mesa and the dielectric sidewall; and
©) in a second plasma stage, providing an energized second etching gas in the chamber and applying a second bias RF power level to the process electrodes and a second source RF power level to the antenna, thereby energizing the second etching gas to etch the semiconductor mesa and a remaining portion of the dielectric sidewall.
A method of etching a substrate in a substrate processing chamber comprising an antenna and process electrodes:
(a) providing a substrate in the chamber, the substrate having a pattern of features, the features comprising a semiconductor mesa covered by a dielectric top wall and dielectric sidewalls,
(b) in a first etching stage, providing in the chamber, an energized first etching gas comprising a halogenated non-hydrogen-containing gas and a halogenated hydrogen-containing gas in a volumetric ratio selected to etch the dielectric top wall to expose the semiconductor mesa; and
©) in a second etching stage, providing in the chamber, an energized second etching gas comprising the halogenated non-hydrogen-containing gas and a chlorine-containing gas in a volumetric ratio selected to etch the semiconductor mesa and the dielectric sidewalls;
(d) in a third etching stage, providing a third etching gas in the chamber and applying a first bias RF power level to the process electrodes and a first source RF power level to the antenna, thereby energizing the third etching gas to further etch the semiconductor mesa and the dielectric sidewalls; and
(e) in a fourth etching stage, providing an energized fourth etching gas in the chamber and applying a second bias RF power level to the process electrodes and a second source RF power level to the antenna, thereby energizing the second etching gas to etch the semiconductor mesa and a remaining portion of the dielectric sidewalls.
A method of etching a substrate in a chamber comprising an antenna and process electrodes, the method comprising:
(a) providing the substrate in the chamber;
(b) in a first stage, providing in the chamber, an energized first etching gas comprising CF
4
and CHF
3
;
©) in a second stage, providing in the chamber, an energized second etching gas comprising CF
4
and Cl
2
;
(d) in a third stage, providing in the chamber, a third etching gas comprising Ar, CF
4
and O
2
, and applying a first bias RF power level to the process electrodes and a first source RF power level to the antenna;
(e) in a fourth stage, providing in the chamber, an energized fourth etching gas comprising Ar and CF
4
, and applying a second bias RF power level to the process electrodes and a second source RF power level to the antenna; and
(f) in a fifth stage, providing in the chamber, an energized fifth etching gas comprising HBr, Cl
2
and HeO
2
.
A method of etching a pattern of features on a substrate in a chamber comprising an antenna and process electrodes, the method comprising:
(a) providing a substrate in the chamber;
(b) in a first stage, providing in the chamber, an energized first etching gas comprising CF
4
and CHF
3
in a volumetric flow ratio of from about 4:1 to about 1:4;
©) in a second stage, providing in the chamber, an energized second etching gas comprising CF
4
and Cl
2
in a volumetric flow ratio of from about 5:1 to about 2:1;
(d) in a third stage, providing in the chamber, a third etching gas comprising Ar, CF
4
and O
2
in a volumetric flow ratio of Ar to (CF
4
and O
2
) of from about 1:1 to about 2:1, applying a first bias RF power level of from about 0 Watts to about 50 Watts to the process electrodes, and applying a first source RF power level of from about 800 to about 1500 Watts to the antenna to energize the third etching gas;
(e) in a fourth stage, providing in the chamber, an energized fourth etching gas comprising Ar and CF
4
in a volumetric flow ratio of from about 8:1 to about 20:1, applying a second bias RF power level to the process electrodes of from about 150 Watts to about 300 Watts, and applying a second source RF power level to the antenna of from about 200 Watts to about 400 Watts to energize the second etching gas; and
(f) in a fifth stage, providing in the chamber, an energized fifth etching gas comprising HBr, Cl
2
and HeO
2
.


REFERENCES:
patent: 4764245 (1988-08-01), Grewal et al.
patent: 5514621 (1996-05-01), Tabara et al.
patent: 5786276 (1998-07-01), Brooks et al.
patent: 5843847 (1998-12-01), Pu et al.
patent: 6133156 (2000-10-01), Langley et al.
patent: 6306710 (2001-10-01), Long et al.

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