Method of etching for integrated circuits with planarized dielec

Details Method of etching for integrated circuits with planarized dielec Method of etching for integrated circuits with planarized dielec

1990-06-27

1991-06-11

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156646, 156651, 156652, 156657, 1566591, 437 40, 437 59, 437200, 437228, B44C 122, C03C 1500, C03C 2506

Patent

active

050229583

ABSTRACT:
An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric.

REFERENCES:
patent: 4532002 (1985-07-01), White
patent: 4816115 (1989-03-01), Horner et al.
patent: 4832789 (1989-05-01), Cochran et al.
patent: 4939105 (1990-07-01), Langley
patent: 4956313 (1990-09-01), Cote et al.
patent: 4966865 (1990-10-01), Welch et al.

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