Method of etching and etch mask

Details Method of etching and etch mask Method of etching and etch mask

2000-02-01

2002-10-01

Gulakowski, Randy (Department: 1746)

Etching a substrate: processes

Masking of a substrate using material resistant to an etchant

Mask is multilayer resist

C216S041000, C216S051000, C438S717000, C438S721000

Reexamination Certificate

active

06458284

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an etching method for use in the manufacture of a semiconductor device and the like and an etch mask for use in the etching method.
2. Description of the Background Art
FIG. 12
is a cross-sectional view of a DRAM including a capacitor having a dielectric film made of a material having a high dielectric constant such as BST (barium strontium titanate). The DRAM comprises MISFETs
18
formed on a semiconductor substrate
13
, and capacitors
19
. Isolation regions
14
and active regions
15
are formed in the semiconductor substrate
13
. MIS gates
16
, contact plugs
4
, a bit line
17
and a interlayer insulation film
5
are formed on the surface of the semiconductor substrate
13
. Each of the MISFETs
18
comprises one MIS gate
16
and two active regions
15
on opposite sides of part of the semiconductor substrate
13
which lies immediately under the MIS gate
16
.
Each of the capacitors
19
comprises an upper electrode
10
, a dielectric layer
9
made of the high dielectric constant material, and a lower electrode
2
connected to its associated active region
15
through a barrier metal layer
3
and a contact plug
4
. The barrier metal layer
3
is formed between the contact plug
4
and the lower electrode
2
for the purpose of preventing adverse effects of contact of the contact plug
4
with the lower electrode
2
upon the lower electrode
2
(e.g., such an effect that when the contact plug
4
is made of polysilicon and the lower electrode
2
is made of metal, the metal in contact with the polysilicon is silicided to increase the resistance value thereof). The barrier metal layer
3
is made of, for example, TiN or TaN. A lower electrode sidewall
8
is formed to prevent the barrier metal layer
3
from contacting the dielectric layer
9
.
In
FIG. 12
, two capacitors
19
are shown as formed in corresponding relationship with two MISFETs
18
, and two lower electrodes
2
, two barrier metal layers
3
and two lower electrode sidewalls
8
are shown as formed in side-by-side relation on opposite sides of the bit line
17
. The dielectric layer
9
and the upper electrode
10
are common to the two capacitors
19
.
An interlayer insulation film
11
is formed on an upper surface of the upper electrode
10
, and an interconnect layer
12
is formed on an upper surface of the interlayer insulation film
11
, as illustrated in FIG.
12
.
The electrodes of the capacitor including the dielectric layer made of the high dielectric constant material are made of, e.g., metal such as Pt (platinum). The electrodes made of such metal may be formed by, e.g., dry etching. However, since the metal such as Pt is inactive to chemical reactions at near room temperature, etching resulting from a chemical reaction does not vigorously occur under etching conditions at near room temperature, but an etching process proceeds almost by the action of physical etching (which etching process is referred to hereinafter as sputter etching).
The procedure of the process of performing sputter etching on the metal such as Pt will be described with reference to
FIGS. 13 through 19
, taking the process of forming the capacitor
19
shown in
FIG. 12
as an example. First, the semiconductor substrate
13
with the interlayer insulation film
5
and the contact plug
4
formed thereon is prepared.
The barrier metal layer material
3
and the lower electrode material
2
(metal such as Pt) stacked in the order named are formed on the surfaces of the interlayer insulation film
5
and the contact plug
4
. A photoresist
6
is formed on the surface of the lower electrode material
2
and patterned using a photolithographic technique (FIG.
13
). Part of the lower electrode material
2
which is not covered with the photoresist
6
is removed by the sputter etching (FIG.
14
).
During the sputter etching, sputtering causes the redeposition of the lower electrode material
2
, and the redeposits are prone to adhere to the photoresist
6
. A redeposit adhering to the upper surface of the photoresist
6
is soon removed by the sputter etching, but a deposit
7
contiguous with the lower electrode
2
is formed on the side surface of the photoresist
6
as shown in FIG.
14
.
Thereafter, part of the barrier metal layer material
3
which is not covered with the photoresist
6
and the lower electrode
2
is removed (FIG.
15
). The remaining photoresist
6
is then removed (FIG.
16
). The deposit
7
which would hinder the lower electrode
2
from functioning as a capacitor electrode is removed by scrubber treatment (FIG.
17
).
The material of the lower electrode sidewall
8
is formed to cover the lower electrode
2
, the barrier metal layer
3
and the interlayer insulation film
5
(FIG.
18
), and is etched back by the sputter etching (FIG.
19
). Thereafter, the dielectric layer
9
and the upper electrode
10
are formed. This completes the capacitor
19
.
However, there has been a likelihood that the reliability of the capacitor decreases to reduce yields in spite of the removal of the deposit
7
for reasons to be described below. In some cases, the deposit
7
is not completely removed by the scrubber treatment, and a residue of the deposit
7
establishes a short circuit, for example, between the upper electrode
10
and the lower electrode
2
. In other cases, traces
7
a
of the deposit
7
remain after the scrubber treatment of the deposit
7
as shown in
FIGS. 17 through 19
to cause electric field concentration during the operation of the capacitor because of their protruding shape, which might induce a leakage current.
To suppress the development of such a deposit
7
, the photoresist
6
should be made as thin as possible for reduction in side surface area thereof. The reduction in side surface area decreases the amount of the redeposit adhering to the photoresist
6
. Further, since the redeposit is less prone to adhere to a top part of the side surface of the photoresist
6
under the influence of the sputter etching performed from above, it can be contemplated that the reduction in the thickness of the photoresist
6
results in the deposit less prone to develop on the side surface of the photoresist
6
.
However, there is a likelihood that the photoresist
6
of the reduced thickness does not function as an etch mask when the lower electrode material
2
is sputter etched. The photoresist is not high in physical strength and is gradually removed as the sputter etching proceeds as shown in
FIGS. 14 and 15
. Thus, the photoresist
6
of the reduced thickness might be completely removed. It is hence difficult to reduce the thickness of the photoresist
6
.
To solve the above problem, it is contemplated to use a physically strong material, rather than the photoresist, as the etch mask (which etch mask is referred to hereinafter as a hard mask). The procedure of the etching process using the hard mask will be described with reference to
FIGS. 20 through 24
, taking the process of forming the capacitor
19
of
FIG. 12
as an example.
First, the semiconductor substrate
13
with the interlayer insulation film
5
and the contact plug
4
formed thereon is prepared. The barrier metal layer material
3
, the lower electrode material
2
and a hard mask material
1
stacked in the order named are formed on the surfaces of the interlayer insulation film
5
and the contact plug
4
. The photoresist
6
is formed on the surface of the hard mask material
1
and patterned using a photolithographic technique (FIG.
20
). Part of the hard mask material
1
which is not covered with the photoresist
6
is removed by dry etching or the like. The photoresist
6
is also removed (FIG.
21
).
Part of the lower electrode material
2
which is not covered with the hard mask material
1
is removed by the sputter etching (FIG.
22
). Thereafter, part of the barrier metal layer material
3
which is not covered with the hard mask material
1
is removed (FIG.
23
). The hard mask
1
is then removed (FIG.
24

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