Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-05-09
2004-07-06
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S717000, C438S736000, C438S719000, C438S734000
Reexamination Certificate
active
06759340
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a method of etching a trench in a silicon-on-insulator (SOI) structure. In particular, the present invention is a method of etching a trench in silicon overlying a dielectric material, where etching is performed using a plasma generated from a combination of a fluorine-containing etchant gas and a passivation gas.
2. Brief Description of the Background Art
Deep trench silicon etching is one of the principal technologies currently being used to fabricate microstructure devices, and is an enabling technology for many microelectromechanical systems (MEMS) applications. Currently, the most commonly used single-crystal silicon deep trench etch process is based upon a cyclic plasma etch/polymer deposition method. The process enables the removal of at least one micron (1 &mgr;m) of silicon per etch cycle. During the etch portion of the etch/deposition process, the principal etchant is often SF
6
, which may be used in combination with a diluent so that the SF
6
concentration in the etchant plasma source gas is about 75% or greater by volume. During the polymer deposition portion of the process, a plasma generated from polymer-forming gases such as CHF
3
is introduced to the chamber to produce polymer coatings on the trench sidewall. The polymer coating helps prevent lateral etching of the trench sidewall during a vertical etch portion of a subsequent cycle.
The cycling of gases in the etch/deposition process introduces a unique type of sidewall roughness known as scalloping.
FIG. 1
shows an open area
104
etched in a silicon substrate
102
to form a silicon trench sidewall
206
exhibiting 0.8 micron deep (d) scallops
108
. Scalloping occurs because the SF
6
etch is relatively isotropic. Because of the discontinuous etch and deposition steps in a silicon etch/polymer deposition process, the etch profile of a single etch step is not flat, but rather it is concave with respect to etched open area
104
. Every etch/deposition cycle leaves a concave scallop
108
on the trench sidewall. This shape is then repeated for each successive etch step, resulting in a sidewall with a wavy, scalloped profile. Scalloping is particularly a problem when the etched trench is to be used as a mold in a subsequent process and when the silicon trench surface is to be used in an optical component.
Another problem which occurs when etching a trench in silicon in an SOI (silicon-on-insulator) structure is known as notching. Notching occurs as the etch front approaches the silicon/dielectric interface. When an etchant gas (such as SF
6
) which has a high selectivity for etching silicon relative to an underlying oxide layer is used during the etch process, etchant species accumulate at the base of the trench. As etching progresses, and there is little or no silicon left at the base of the trench to be etched in a vertical direction, lateral etching into the silicon sidewall at the bottom of the trench continues, resulting in a severely undercut, notched profile at the base of the trench. Notching is particularly a problem when etching closely spaced trenches. If notching is severe, the bases of adjacent trenches could be joined. Such joining at the bottom of the trenches leads to subsequent device failure.
FIG. 2
shows a cross-sectional schematic of closely spaced, adjacent trenches
210
,
220
, which have been formed in a silicon substrate
202
overlying a dielectric material
200
. Trenches
210
and
220
have been joined at their respective bases
212
,
222
, due to severe notching as a result of a silicon trench etch process. The sidewalls
214
,
224
of trenches
210
and
220
also exhibit scalloping.
SUMMARY OF THE INVENTION
We have developed a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench.
In one embodiment of the method, a first portion of a trench is etched by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. The fluorine-containing gas typically comprises at least 70 volume % of the plasma source gas used during etching. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The desired depth of the first portion of the trench is typically dependent on the final desired trench depth. For relatively shallow trenches, the depth of the first portion of the trench is typically at least 50%, and more typically, at least 70%, of the final desired trench depth. For deeper trenches, the depth of the first portion of the trench is typically about 90% of the final desired trench depth.
The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas. The volumetric ratio of the fluorine-containing gas to the polymer-forming gas is typically within the range of about 1:1 to about 20:1, and more typically, within the range of about 8:1 to about 10:1.
The fluorine-containing gas used during etching is typically SF
6
, CF
4
, NF
3
, or a combination thereof, and is most typically SF
6
. The polymer-forming gas is typically, but not limited to, a carbon-containing gas, such as C
4
F
8
, CH
2
F
2
, CHF
3
, or CF
4
. During the polymer deposition step, the polymer-forming gas may also be HBr or other compounds capable of reacting with silicon to form a polymer. However, during the combined etching/passivation step, we recommend the use of a carbon-containing compound as the polymer-forming gas.
The combined etching/passivation step successfully eliminates notching at the interface of the silicon substrate and the underlying dielectric.
In an alternative embodiment of the method, the entire trench depth is etched by exposing the silicon, through a patterned masking layer, to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas. The silicon etch rate is slower with the single-step embodiment than with the embodiment described above. Also, the selectivity for etching silicon relative to an overlying photoresist masking layer is lower with the single-step embodiment. Therefore, the depth of trenches which may be etched using the single-step embodiment is typically limited by the thickness of the photoresist layer which can be applied.
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Khan Anisul H.
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